Robust gate sizing via mean excess delay minimization. - Jason Cong; John Lee 002; Lieven Vandenberghe (ISPD, 2008)

On the futility of statistical power optimization. - Jason Cong; Puneet Gupta 001; John Lee 002 (ASP-DAC, 2009)

Incremental gate sizing for late process changes. - John Lee 002; Puneet Gupta 001 (ICCD, 2010)

Evaluating Statistical Power Optimization. - Jason Cong; Puneet Gupta 001; John Lee 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A unified optimization framework for simultaneous gate sizing and placement under density constraints. - Jason Cong; John Lee 002; Guojie Luo (ISCAS, 2011)

Impact of range and precision in technology on cell-based design. - John Lee 002; Puneet Gupta 001 (ICCAD, 2012)

Parametric Hierarchy Recovery in Layout Extracted Netlists. - John Lee 002; Puneet Gupta 001; Fedor Pikus (ISVLSI, 2012)

Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment. - John Lee 002; Puneet Gupta 001 (Found. Trends Electron. Des. Autom., 2012)

ECO cost measurement and incremental gate sizing for late process changes. - John Lee 002; Puneet Gupta 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Discrete sizing for leakage power optimization in physical design: A comparative study. - Santiago Mok; John Lee 002; Puneet Gupta 001 (ACM Trans. Design Autom. Electr. Syst., 2012)