Linear decomposition algorithm for VLSI design applications. - Jianmin Li; John Lillis; Chung-Kuan Cheng (ICCAD, 1995)

New Spectral Linear Placement and Clustering Approach. - Jianmin Li; John Lillis; Lung-Tien Liu; Chung-Kuan Cheng (DAC, 1996)

New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. - John Lillis; Chung-Kuan Cheng; Ting-Ting Y. Lin; Chin-Yen Ho (DAC, 1996)

Simultaneous Routing and Buffer Insertion for High Performance Interconnect. - John Lillis; Chung-Kuan Cheng; Ting-Ting Y. Lin (Great Lakes Symposium on VLSI, 1996)

Optimal wire sizing and buffer insertion for low power and a generalized delay model. - John Lillis; Chung-Kuan Cheng; Ting-Ting Y. Lin (IEEE J. Solid State Circuits, 1996)

A new layout-driven timing model for incremental layout optimization. - Fang-Jou Liu; John Lillis; Chung-Kuan Cheng (ASP-DAC, 1997)

Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. - John Lillis; Chung-Kuan Cheng (DAC, 1997)

Table-Lookup Methods for Improved Performance-Driven Routing. - John Lillis; Premal Buch (DAC, 1998)

Timing optimization for multisource nets: characterization andoptimal repeater insertion. - John Lillis; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

MONGREL: Hybrid Techniques for Standard Cell Placement. - Sung-Woo Hur; John Lillis (ICCAD, 2000)

Timing-driven maze routing. - Sung-Woo Hur; Ashok Jagannathan; John Lillis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Buffered Steiner trees for difficult instances. - Charles J. Alpert; Milos Hrkic; Jiang Hu; Andrew B. Kahng; John Lillis; Bao Liu 001; Stephen T. Quay; Sachin S. Sapatnekar; A. J. Sullivan; Paul Villarrubia (ISPD, 2001)

S-Tree: a technique for buffered routing tree synthesis. - Milos Hrkic; John Lillis (DAC, 2002)

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. - Milos Hrkic; John Lillis (ISPD, 2002)

A fast algorithm for context-aware buffer insertion. - Ashok Jagannathan; Sung-Woo Hur; John Lillis (ACM Trans. Design Autom. Electr. Syst., 2002)

Relaxation and Clustering in a Local Search Framework: Application to Linear Placement. - Sung-Woo Hur; John Lillis (VLSI Design, 2002)

Timing optimization of FPGA placements by logic replication. - Giancarlo Beraudo; John Lillis (DAC, 2003)

Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. - Milos Hrkic; John Lillis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

On interactions between routing and detailed placement. - Devang Jariwala; John Lillis (ICCAD, 2004)

An LP-based methodology for improved timing-driven placement. - Qingzhou (Ben) Wang; John Lillis; Shubhankar Sanyal (ASP-DAC, 2005)

A study of tighter lower bounds in LP relaxation based placement. - Qingzhou (Ben) Wang; Devang Jariwala; John Lillis (ACM Great Lakes Symposium on VLSI, 2005)

Techniques for improved placement-coupled logic replication. - Hosung (Leo) Kim; John Lillis; Milos Hrkic (ACM Great Lakes Symposium on VLSI, 2006)

Trunk decomposition based global routing optimization. - Devang Jariwala; John Lillis (ICCAD, 2006)

An Approach to Placement-Coupled Logic Replication. - Milos Hrkic; John Lillis; Giancarlo Beraudo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. - Jianhua Liu; Yi Zhu 002; Haikun Zhu; Chung-Kuan Cheng; John Lillis (ASP-DAC, 2007)

Repeater insertion for concurrent setup and hold time violations with power-delay trade-off. - Salim Chowdhury; John Lillis (ISPD, 2007)

RBI: Simultaneous Placement and Routing Optimization Technique. - Devang Jariwala; John Lillis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A framework for layout-level logic restructuring. - Hosung (Leo) Kim; John Lillis (ISPD, 2008)

A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs. - Hosung Kim; John Lillis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Generalized Buffer Insertion. - Milos Hrkic; John Lillis (Handbook of Algorithms for Physical Design Automation, 2008)

Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming. - Marco Rabozzi; John Lillis; Marco D. Santambrogio (FCCM, 2014)

Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation. - Marco Rabozzi; Gianluca Carlo Durelli; Antonio Miele; John Lillis; Marco Domenico Santambrogio (IEEE Trans. Very Large Scale Integr. Syst., 2017)