The circuit and physical design of the POWER4 microprocessor. - James D. Warnock; John M. Keaty; John G. Petrovick; Joachim G. Clabes; Charles J. Kircher; Byron Krauter; Phillip J. Restle; Brian A. Zoric; Carl J. Anderson (IBM J. Res. Dev., 2002)

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. - Dac C. Pham; Erwin Behnen; Mark Bolliger; H. Peter Hofstee; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; Yoshio Masubuchi; Stephen D. Posluszny; Mack W. Riley; et al. (CICC, 2005)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. - Dac C. Pham; Tony Aipperspach; David Boerstler; Mark Bolliger; Rajat Chaudhry; Dennis Cox; Paul E. Harvey; H. Peter Hofstee; Charles R. Johns; Jim Kahle; Atsushi Kameyama; John M. Keaty; et al. (IEEE J. Solid State Circuits, 2006)

Implementation of the 65nm Cell Broadband Engine. - Mack W. Riley; Brian K. Flachs; Sang H. Dhong; Gilles Gervais; Steve Weitzel; Michael Wang 001; David Boerstler; Mark Bolliger; John M. Keaty; Jürgen Pille; R. Berry; Osamu Takahashi; et al. (CICC, 2007)

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. - Steven C. Chan; Phillip J. Restle; Thomas J. Bucelot; John S. Liberty; Stephen Weitzel; John M. Keaty; Brian K. Flachs; Richard Volant; Peter Kapusta; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2009)