MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications. - B. E. Duewer; John M. Wilson 002; D. A. Winick; Paul D. Franzon (ARVLSI, 1999)

4 Gbps high-density AC coupled interconnection. - Stephen E. Mick; John M. Wilson 002; Paul D. Franzon (CICC, 2002)

Simplified delay design guidelines for on-chip global interconnects. - Liang Zhang 038; Wentai Liu; Rizwan Bashirullah; John M. Wilson 002; Paul D. Franzon (ACM Great Lakes Symposium on VLSI, 2004)

Driver pre-emphasis techniques for on-chip global buses. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (ISLPED, 2005)

Demystifying 3D ICs: The Pros and Cons of Going Vertical. - W. Rhett Davis; John M. Wilson 002; Stephen E. Mick; Jian Xu; Hao Hua; Christopher Mineo; Ambarish M. Sule; Michael B. Steer; Paul D. Franzon (IEEE Des. Test Comput., 2005)

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver. - Lei Luo 006; John M. Wilson 002; Stephen E. Mick; Jian Xu; Liang Zhang 038; Evan Erickson; Paul D. Franzon (CICC, 2006)

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (CICC, 2006)

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. - Lei Luo 006; John M. Wilson 002; Stephen E. Mick; Jian Xu; Liang Zhang 038; Paul D. Franzon (IEEE J. Solid State Circuits, 2006)

Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling. - Liang Zhang 038; John M. Wilson 002; Rizwan Bashirullah; Lei Luo 006; Jian Xu; Paul D. Franzon (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications. - Paul D. Franzon; John M. Wilson 002; Ming Li (3DIC, 2010)

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. - Brian S. Leibowitz; Robert Palmer; John Poulton; Yohan Frans; Simon Li; John M. Wilson 002; Michael Bucher; Andrew M. Fuller; John G. Eyles; Marko Aleksic; Trey Greer; Nhat Nguyen (IEEE J. Solid State Circuits, 2010)

Power-efficient I/O design considerations for high-bandwidth applications. - John C. Eble; Scott Best; Brian S. Leibowitz; Lei Luo 006; Robert Palmer; John M. Wilson 002; Jared Zerbe; Amir Amirkhany; Nhat Nguyen (CICC, 2011)

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. - John W. Poulton; William J. Dally; Xi Chen 033; John G. Eyles; Thomas H. Greer; Stephen G. Tell; John M. Wilson 002; C. Thomas Gray (IEEE J. Solid State Circuits, 2013)

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. - John M. Wilson 002; Matthew R. Fojtik; John W. Poulton; Xi Chen 033; Stephen G. Tell; Thomas H. Greer; C. Thomas Gray; William J. Dally (ISSCC, 2016)

A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. - Laura Fick; Dennis Sylvester; John W. Poulton; John M. Wilson 002; C. Thomas Gray (ISCAS, 2017)

Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. - Mike O'Connor; Niladrish Chatterjee; Donghyuk Lee; John M. Wilson 002; Aditya Agrawal; Stephen W. Keckler; William J. Dally (MICRO, 2017)

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. - Sudhir S. Kudva; Sanquan Song; John W. Poulton; John M. Wilson 002; Wenxu Zhao; C. Thomas Gray (CICC, 2018)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

Hardware-Enabled Artificial Intelligence. - William J. Dally; C. Thomas Gray; John Poulton; Brucek Khailany; John M. Wilson 002; Larry R. Dennison (VLSI Circuits, 2018)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. - Walker J. Turner; John W. Poulton; Yoshinori Nishi; Xi Chen 033; Brian Zimmer; Sanquan Song; John M. Wilson 002; William J. Dally; C. Thomas Gray (CICC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)