Exploring Potential Parallelism of Sequential Programs with Superblock Reordering. - John M. Ye; Tianzhou Chen (HPCC-ICESS, 2012)

Regional cache organization for NoC based many-core processors. - John M. Ye; Man Cao; Zening Qu; Tianzhou Chen (J. Comput. Syst. Sci., 2013)

Offline Data Dependence Analysis to Facilitate Runtime Parallelism Extraction. - John M. Ye; Jason Chen; Tianzhou Chen; Minghui Wu 001; Li Liu 006 (CSE, 2014)

Core Affinity Code Block Schedule to Reduce Inter-core Data Synchronization of SpMT. - John M. Ye; Songyuan Li; Tianzhou Chen; Minghui Wu 001; Li Liu 006 (HPCC/CSS/ICESS, 2014)

Conflict-Free Code Block Scheduling to Hide SpMT Inter-Core Register Sync Delay. - John M. Ye; Jason Chen; Tianzhou Chen; Qingsong Shi (PDCAT, 2014)

SimLuator: A multi-core CPU simulator with dynamic language Lua. - John M. Ye; Songyuan Li; Tianzhou Chen; Minghui Wu 001; Li Liu 006 (SIMULTECH, 2014)

Potential thread-level-parallelism exploration with superblock reordering. - John M. Ye; Hui Yan; Honglun Hou; Tianzhou Chen (Computing, 2014)

Shared Write Buffer to Support Speculative Execution. - John M. Ye; Hongjun Dai; Songyuan Li; Tianzhou Chen (HPCC/CSS/ICESS, 2015)

Shared Write Buffer to Support Data Sharing Among Speculative Multi-threading Cores. - John M. Ye; Songyuan Li; Tianzhou Chen (HPCC/CSS/ICESS, 2015)

MCMG simulator: A unified simulation framework for CPU and graphic GPU. - Jianliang Ma; Licheng Yu; John M. Ye; Tianzhou Chen (J. Comput. Syst. Sci., 2015)

Shared write buffer to boost applications on SpMT architecture. - Ming Chen; John M. Ye; Tianzhou Chen; Hongjun Dai (J. Supercomput., 2017)