A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. - Kuan Zhou; Michael Chu; Chao You; Jong-Ru Guo; Channakeshav; John Mayega; John F. McDonald 001; Russell P. Kraft; Bryan S. Goda (FPGA, 2003)

3D direct vertical interconnect microprocessors test vehicle. - John Mayega; Okan Erdogan; Paul M. Belemjian; Kuan Zhou; John F. McDonald 001; Russell P. Kraft (ACM Great Lakes Symposium on VLSI, 2003)

Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques. - Kuan Zhou; Jong-Ru Guo; Chao You; John Mayega; Russell P. Kraft; T. Zhang; John F. McDonald 001; Bryan S. Goda (J. Circuits Syst. Comput., 2005)