Sequential Redundancy Identification Using Verification Techniques. - John Moondanos; Jacob A. Abraham (ITC, 1992)

Abstraction of data path registers for multilevel verification of large circuits. - Yatin Vasant Hoskote; John Moondanos; Jacob A. Abraham; Donald S. Fussell (Great Lakes Symposium on VLSI, 1994)

Verification of Circuits Described in VHDL through Extraction of Design Intent. - Yatin Vasant Hoskote; John Moondanos; Jacob A. Abraham; Donald S. Fussell (VLSI Design, 1994)

Automatic verification of implementations of large circuits against HDL specifications. - Yatin Vasant Hoskote; Jacob A. Abraham; Donald S. Fussell; John Moondanos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. - John Moondanos; Carl-Johan H. Seger; Ziyad Hanna; Daher Kaiss (CAV, 2001)

An enhanced cut-points algorithm in formal equivalence verification. - Zurab Khasidashvili; John Moondanos; Daher Kaiss; Ziyad Hanna (HLDVT, 2001)

TRANS: efficient sequential verification of loop-free circuits. - Zurab Khasidashvili; John Moondanos; Ziyad Hanna (HLDVT, 2002)

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. - Feng Lu 002; Li-C. Wang; Kwang-Ting Cheng; John Moondanos; Ziyad Hanna (DAC, 2003)

Preserving synchronizing sequences of sequential circuits after retiming. - Maher N. Mneimneh; Karem A. Sakallah; John Moondanos (ASP-DAC, 2004)

A Signal Correlation Guided Circuit-SAT Solver. - Feng Lu 002; Li-C. Wang; Kwang-Ting (Tim) Cheng; John Moondanos; Ziyad Hanna (J. Univers. Comput. Sci., 2004)

JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study. - Abhijit Davare; Qi Zhu 002; John Moondanos; Alberto L. Sangiovanni-Vincentelli (ESTIMedia, 2005)

Generation of shorter sequences for high resolution error diagnosis using sequential SAT. - Sung-Jui (Song-Ra) Pan; Kwang-Ting Cheng; John Moondanos; Ziyad Hanna (ASP-DAC, 2006)

From Error to Error: Logic Debugging in the Many-Core Era. - John Moondanos (V&D@FLoC, 2006)

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability. - Feijun Zheng; Kwang-Ting Cheng; Xiaolang Yan; John Moondanos; Ziyad Hanna (ATS, 2007)

Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis. - Nestoras E. Evmorfopoulos; Maria-Aikaterini Rammou; George I. Stamoulis; John Moondanos (ICCAD, 2010)

A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine. - Michael K. Tsiampas; Nestor E. Evmorfopoulos; Konstantis Daloukas; John Moondanos; Georgios I. Stamoulis (DTIS, 2018)