A Study of Digital Network Structure and Its Relation to Fault Diagnosis - John Patrick Hayes (1970)

A Nand Model ror Fault Diagnosis in Combinational Logic Networks. - John P. Hayes (IEEE Trans. Computers, 1971)

On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests. - John P. Hayes (IEEE Trans. Computers, 1971)

Minimization of Fanout in Switching Networks - John P. Hayes (SWAT, 1974)

On Modifying Logic Networks to Improve Their Diagnosability. - John P. Hayes (IEEE Trans. Computers, 1974)

Test Point Placement to Simplify Fault Detection. - John P. Hayes; Arthur D. Friedman (IEEE Trans. Computers, 1974)

The Fanout Structure of Switching Functions. - John P. Hayes (J. ACM, 1975)

Detection of Pattern-Sensitive Faults in Random-Access Memories. - John P. Hayes (IEEE Trans. Computers, 1975)

Partitioning logic circuits to maximize fault resolution. - Ayee Goundan; John P. Hayes (DAC, 1976)

Enumeration of Fanout-Free Boolean Functions. - John P. Hayes (J. ACM, 1976)

Transition Count Testing of Combinational Logic Circuits. - John P. Hayes (IEEE Trans. Computers, 1976)

A Graph Model for Fault-Tolerant Computing Systems. - John P. Hayes (IEEE Trans. Computers, 1976)

On the Properties of Irredundant Logic Networks. - John P. Hayes (IEEE Trans. Computers, 1976)

Generation of Optimal Transition Count Tests. - John P. Hayes (IEEE Trans. Computers, 1978)

Path Complexity of Logic Networks. - John P. Hayes (IEEE Trans. Computers, 1978)

Fault Tolerance of a Class of Connecting Networks. - John Paul Shen; John P. Hayes (ISCA, 1980)

Testability Considerotions in Microprocessor-Based Design. - John P. Hayes; Edward J. McCluskey (Computer, 1980)

Design of Totally Fault Locatable Combinational Networks. - Ayee Goundan; John P. Hayes (IEEE Trans. Computers, 1980)

Identification of Equivalent Faults in Logic Networks. - Ayee Goundan; John P. Hayes (IEEE Trans. Computers, 1980)

Testing Memories for Single-Cell Pattern-Sensitive Faults. - John P. Hayes (IEEE Trans. Computers, 1980)

A Functional Approach to Testing Bit-Sliced Microprocessors. - Thirumalai Sridhar; John P. Hayes (IEEE Trans. Computers, 1981)

Design of Easily Testable Bit-Sliced Systems. - Thirumalai Sridhar; John P. Hayes (IEEE Trans. Computers, 1981)

A fault simulation methodology for VLSI. - John P. Hayes (DAC, 1982)

An experimental MOS fault simulation program CSASIM. - Masato Kawai; John P. Hayes (DAC, 1984)

Fault-Tolerance of Dynamic-Full-Access Interconnection Networks. - John Paul Shen; John P. Hayes (IEEE Trans. Computers, 1984)

Fault Modeling for Digital MOS Integrated Circuits. - John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Architecture of a Hypercube Supercomputer. - John P. Hayes; Trevor N. Mudge; Quentin F. Stout (ICPP, 1986)

Analysis of Multiple-Bus Interconnection Networks. - Trevor N. Mudge; John P. Hayes; Gregory D. Buzzard; Donald C. Winsor (J. Parallel Distributed Comput., 1986)

A Microprocessor-based Hypercube Supercomputer. - John P. Hayes; Trevor N. Mudge; Quentin F. Stout; Stephen Colley; John Palmer (IEEE Micro, 1986)

Fault-tolerance and performance analysis of beta-networks. - John Paul Shen; John P. Hayes; Luigi Ciminiera; Angelo Serra (Parallel Comput., 1986)

Uncertainty, Energy, and Multiple-Valued Logics. - John P. Hayes (IEEE Trans. Computers, 1986)

Pseudo-Boolean Logic Circuits. - John P. Hayes (IEEE Trans. Computers, 1986)

An Array Layout Methodology for VLlSI Circuits. - Musaravakkam S. Krishnan; John P. Hayes (IEEE Trans. Computers, 1986)

Distributed Recovery in Fault-Tolerant Multiprocessor Networks. - Raif M. Yanney; John P. Hayes (IEEE Trans. Computers, 1986)

Digital Simulation with Multiple Logic Values. - John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

Layout Optimization of CMOS Functional Cells. - R. L. Maiasz; John P. Hayes (DAC, 1987)

Multiple Bus Architectures. - Trevor N. Mudge; John P. Hayes; Donald C. Winsor (Computer, 1987)

An Introduction to Switch-Level Modeling. - John P. Hayes (IEEE Des. Test, 1987)

On allocating subcubes in a hypercube multiprocessor. - Shantanu Dutt; John P. Hayes (C³P, 1988)

Routing and broadcasting in faulty hypercube computers. - Tze Chiang Lee; John P. Hayes (C³P, 1988)

Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures. - Shantanu Dutt; John P. Hayes (FTCS, 1988)

Logic simulation on vector processors. - Ram Raghavan; John P. Hayes; William R. Martin (ICCAD, 1988)

Fault Recovery in Distributed Processing Loop Networks. - Raif M. Yanney; John P. Hayes (Comput. Networks, 1988)

A normalized-area measure for VLSI layouts. - Musaravakkam S. Krishnan; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Implementation of VLSI self-testing by regularization. - Y. You; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

An automorphic approach to the design of fault-tolerant multiprocessors. - Shantanu Dutt; John P. Hayes (FTCS, 1989)

Magnitude classes in switch-level modeling. - Eduard Cerny; John P. Hayes; Nicholas C. Rumin (ICCD, 1989)

High-Level Test Generation for VLSI. - Debashis Bhattacharya; Brian T. Murray; John P. Hayes (Computer, 1989)

Hypercube supercomputers. - John P. Hayes; Trevor N. Mudge (Proc. IEEE, 1989)

On randomly interleaved memories. - Ram Raghavan; John P. Hayes (SC, 1990)

A hierarchical test generation methodology for digital circuits. - Debashis Bhattacharya; John P. Hayes (J. Electron. Test., 1990)

On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. - Shantanu Dutt; John P. Hayes (IEEE Trans. Computers, 1990)

Designing for high-level test generation. - Debashis Bhattacharya; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Layout optimization of static CMOS functional cells. - Robert L. Maziasz; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Hierarchical test generation using precomputed tests for modules. - Brian T. Murray; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Exact Width and Height Minimization of CMOS Cells. - Robert L. Maziasz; John P. Hayes (DAC, 1991)

Scalar-Vector Memory Interference in Vector Computers. - Ram Raghavan; John P. Hayes (ICPP (1), 1991)

Test Propagation Through Modules and Circuits. - Brian T. Murray; John P. Hayes (ITC, 1991)

Designing Fault-Tolerant System Using Automorphisms. - Shantanu Dutt; John P. Hayes (J. Parallel Distributed Comput., 1991)

Subcube Allocation in Hypercube Computers. - Shantanu Dutt; John P. Hayes (IEEE Trans. Computers, 1991)

Test-Set Preserving Logic Transformations. - Michael J. Batek; John P. Hayes (DAC, 1992)

Design of Gracefully Degradable Hypercube-Connected Systems. - Tze Chiang Lee; John P. Hayes (J. Parallel Distributed Comput., 1992)

Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. - Shantanu Dutt; John P. Hayes (IEEE Trans. Computers, 1992)

A Fault-Tolerant Communication Scheme for Hypercube Computers. - Tze Chiang Lee; John P. Hayes (IEEE Trans. Computers, 1992)

Accuracy of magnitude-class calculations in switch-level modeling. - Eduard Cerny; John P. Hayes; Nicholas C. Rumin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Efficient Testing of Tree Circuits. - Ronald D. Blanton; John P. Hayes (FTCS, 1993)

Balance Testing of Logic Circuits. - Krishnendu Chakrabarty; John P. Hayes (FTCS, 1993)

Aliasing-free error detection (ALFRED). - Krishnendu Chakrabarty; John P. Hayes (VTS, 1993)

Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories. - Pinaki Mazumder; John P. Hayes (IEEE Des. Test Comput., 1993)

Edge fault tolerance in graphs. - Frank Harary; John P. Hayes (Networks, 1993)

Reducing Inerference Among Vector Accesses in Interleaved Memories. - Ram Raghavan; John P. Hayes (IEEE Trans. Computers, 1993)

DFBT: A Design-for-Testability Method Based on Balance Testing. - Krishnendu Chakrabarty; John P. Hayes (DAC, 1994)

Connectivity and Fault Tolerance of Multiple-Bus Systems. - Hung-Kuei Ku; John P. Hayes (FTCS, 1994)

Structural fault tolerance in VLSI-based systems. - Hung-Kuei Ku; John P. Hayes (Great Lakes Symposium on VLSI, 1994)

Efficient Test-Response Compression for Multiple-Output Cicuits. - Krishnendu Chakrabarty; John P. Hayes (ITC, 1994)

Optimal Testing and Design of Adders. - Michael J. Batek; John P. Hayes (VLSI Design, 1994)

Design verification via simulation and automatic test pattern generation. - Hussain Al-Asaad; John P. Hayes (ICCAD, 1995)

Technology mapping for field-programmable gate arrays using integer programming. - Amit Chowdhary; John P. Hayes (ICCAD, 1995)

Hierarchical timing analysis using conditional delays. - Hakan Yalcin; John P. Hayes (ICCAD, 1995)

Optimal Space Compaction of Test Responses. - Krishnendu Chakrabarty; Brian T. Murray; John P. Hayes (ITC, 1995)

High-Level Test Generation Using Symbolic Scheduling. - Mark C. Hansen; John P. Hayes (ITC, 1995)

High-level test generation using physically-induced faults. - Mark C. Hansen; John P. Hayes (VTS, 1995)

Cumulative balance testing of logic circuits. - Krishnendu Chakrabarty; John P. Hayes (IEEE Trans. Very Large Scale Integr. Syst., 1995)

XPRESS: A Cell Layout Generator with Integrated Transistor Folding. - Avaneendra Gupta; Siang-Chun The; John P. Hayes (ED&TC, 1996)

Width minimization of two-dimensional CMOS cells using integer programming. - Avaneendra Gupta; John P. Hayes (ICCAD, 1996)

An approximate timing analysis method for datapath circuits. - Hakan Yalcin; John P. Hayes; Karem A. Sakallah (ICCAD, 1996)

Design of a fast, easily testable ALU. - R. D. (Shawn) Blanton; John P. Hayes (VTS, 1996)

Testing ICs: Getting to the Core of the Problem. - Brian T. Murray; John P. Hayes (Computer, 1996)

Balance testing and balance-testable design of logic circuits. - Krishnendu Chakrabarty; John P. Hayes (J. Electron. Test., 1996)

Node fault tolerance in graphs. - Frank Harary; John P. Hayes (Networks, 1996)

Optimally edge fault-tolerant trees. - Hung-Kuei Ku; John P. Hayes (Networks, 1996)

Testability of Convergent Tree Circuits. - Ronald D. Blanton; John P. Hayes (IEEE Trans. Computers, 1996)

Test response compaction using multiplexed parity trees. - Krishnendu Chakrabarty; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. - Avaneendra Gupta; John P. Hayes (DAC, 1997)

The input pattern fault model and its application. - Ronald D. Blanton; John P. Hayes (ED&TC, 1997)

General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. - Amit Chowdhary; John P. Hayes (FPGA, 1997)

A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. - Avaneendra Gupta; John P. Hayes (VLSI Design, 1997)

Testability Properties of Divergent Trees. - R. D. (Shawn) Blanton; John P. Hayes (J. Electron. Test., 1997)

Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses. - Hung-Kuei Ku; John P. Hayes (IEEE Trans. Computers, 1997)

On the quality of accumulator-based compaction of test responses. - Krishnendu Chakrabarty; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Event propagation conditions in circuit delay computation. - Hakan Yalcin; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 1997)

Connective Fault Tolerance in Multiple-Bus Systems. - Hung-Kuei Ku; John P. Hayes (IEEE Trans. Parallel Distributed Syst., 1997)

Optimal 2-D cell layout with integrated transistor folding. - Avaneendra Gupta; John P. Hayes (ICCAD, 1998)

High-coverage ATPG for datapath circuits with unimplemented blocks. - HyungWon Kim 001; John P. Hayes (ITC, 1998)

Online BIST for Embedded Systems. - Hussain Al-Asaad; Brian T. Murray; John P. Hayes (IEEE Des. Test Comput., 1998)

Scalable Test Generators for High-Speed Datapath Circuits. - Hussain Al-Asaad; John P. Hayes; Brian T. Murray (J. Electron. Test., 1998)

Optimal Zero-Aliasing Space Compaction of Test Responses. - Krishnendu Chakrabarty; Brian T. Murray; John P. Hayes (IEEE Trans. Computers, 1998)

High-level design verification of microprocessors via error modeling. - David Van Campenhout; Hussain Al-Asaad; John P. Hayes; Trevor N. Mudge; Richard B. Brown (ACM Trans. Design Autom. Electr. Syst., 1998)

Zero-aliasing space compaction of test responses using multiple parity signatures. - Krishnendu Chakrabarty; John P. Hayes (IEEE Trans. Very Large Scale Integr. Syst., 1998)

High-Level Test Generation for Design Verification of Pipelined Microprocessors. - David Van Campenhout; Trevor N. Mudge; John P. Hayes (DAC, 1999)

Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. - Nagarajan Kandasamy; John P. Hayes; Brian T. Murray (SRDS, 1999)

Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. - Avaneendra Gupta; John P. Hayes (VLSI Design, 1999)

Delay Fault Testing of Designs with Embedded IP Cores. - HyungWon Kim 001; John P. Hayes (VTS, 1999)

Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. - Mark C. Hansen; Hakan Yalcin; John P. Hayes (IEEE Des. Test Comput., 1999)

ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. - Hussain Al-Asaad; John P. Hayes (VTS, 2000)

Collection and Analysis of Microprocessor Design Errors. - David Van Campenhout; Trevor N. Mudge; John P. Hayes (IEEE Des. Test Comput., 2000)

Logic Design Validation via Simulation and Automatic Test Pattern Generation. - Hussain Al-Asaad; John P. Hayes (J. Electron. Test., 2000)

CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. - Avaneendra Gupta; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2000)

On the design of fast, easily testable ALU's. - Ronald D. Blanton; John P. Hayes (IEEE Trans. Very Large Scale Integr. Syst., 2000)

An Advanced Timing Characterization Method Using Mode Dependency. - Hakan Yalcin; Robert Palermo; Mohammad Mortazavi; Cyrus Bamji; Karem A. Sakallah; John P. Hayes (DAC, 2001)

A fault model for function and delay testing. - Joonhwan Yi; John P. Hayes (ETW, 2001)

Realization-independent ATPG for designs with unimplemented blocks. - HyungWon Kim 001; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Fast and accurate timing characterization using functionalinformation. - Hakan Yalcin; Mohammad Mortazavi; Robert Palermo; Cyrus Bamji; Karem A. Sakallah; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Delay fault testing of IP-based designs via symbolic path modeling. - HyungWon Kim 001; John P. Hayes (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Time-Constrained Failure Diagnosis in Distributed Embedded Systems. - Nagarajan Kandasamy; John P. Hayes; Brian T. Murray (DSN, 2002)

Fault-Tolerant Quantum Computers. - John P. Hayes (IPDPS, 2002)

Reversible Logic Circuit Synthesis. - Vivek V. Shende; Aditya K. Prasad; Igor L. Markov; John P. Hayes (IWLS, 2002)

Guest Editorial. - Dimitris Nikolos; John P. Hayes; Michael Nicolaidis; Cecilia Metra (J. Electron. Test., 2002)

General technology mapping for field-programmable gate arrays based on lookup tables. - Amit Chowdhary; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2002)

Gate-level simulation of quantum circuits. - George F. Viamontes; Manoj Rajagopalan; Igor L. Markov; John P. Hayes (ASP-DAC, 2003)

Tutorial: basic concepts in quantum circuits. - John P. Hayes (DAC, 2003)

Low-Cost On-Line Fault Detection Using Control Flow Assertions. - Rajesh Venkatasubramanian; John P. Hayes; Brian T. Murray (IOLTS, 2003)

ILP-based optimization of sequential circuits for low power. - Feng Gao 017; John P. Hayes (ISLPED, 2003)

On-Line Monitor Design of Finite-State Machines. - Feng Gao 017; John P. Hayes (J. Electron. Test., 2003)

Improving Gate-Level Simulation of Quantum Circuits. - George F. Viamontes; Igor L. Markov; John P. Hayes (Quantum Inf. Process., 2003)

Synthesis of reversible logic circuits. - Vivek V. Shende; Aditya K. Prasad; Igor L. Markov; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

On the properties of the input pattern fault model. - Ronald D. Blanton; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2003)

Testing for Missing-Gate Faults in Reversible Circuits. - John P. Hayes; Ilia Polian; Bernd Becker 001 (Asian Test Symposium, 2004)

High-Performance QuIDD-Based Simulation of Quantum Circuits. - George F. Viamontes; Igor L. Markov; John P. Hayes (DATE, 2004)

Discovering 1-FT Routes in Mobile Ad Hoc Networks. - Rajesh Venkatasubramanian; John P. Hayes (DSN, 2004)

Self-Optimization in Computer Systems via On-Line Control: Application to Power Management. - Nagarajan Kandasamy; Sherif Abdelwahed; John P. Hayes (ICAC, 2004)

Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. - Feng Gao 017; John P. Hayes (ICCD, 2004)

Fault testing for reversible circuits. - Ketan N. Patel; John P. Hayes; Igor L. Markov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Faults and Tests in Quantum Circuits. - John P. Hayes (Asian Test Symposium, 2005)

A Family of Logical Fault Models for Reversible Circuits. - Ilia Polian; Thomas Fiehn; Bernd Becker 001; John P. Hayes (Asian Test Symposium, 2005)

An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management. - Nagarajan Kandasamy; Sherif Abdelwahed; Gregory C. Sharp; John P. Hayes (Self-star Properties in Complex Information Systems, 2005)

A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. - Jia-Yi Chen; Michael P. Flynn; John P. Hayes (CICC, 2005)

Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. - Feng Gao 017; John P. Hayes (DAC, 2005)

Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. - Smita Krishnaswamy; George F. Viamontes; Igor L. Markov; John P. Hayes (DATE, 2005)

Logic circuit testing for transient faults. - Smita Krishnaswamy; Igor L. Markov; John P. Hayes (ETS, 2005)

Transient fault characterization in dynamic noisy environments. - Ilia Polian; John P. Hayes; Sandip Kundu; Bernd Becker 001 (ITC, 2005)

Impact of mobility on connection in ad hoc networks. - Sungsoon Cho; John P. Hayes (WCNC, 2005)

Is quantum search practical? - George F. Viamontes; Igor L. Markov; John P. Hayes (Comput. Sci. Eng., 2005)

The Coupling Model for Function and Delay Faults. - Joonhwan Yi; John P. Hayes (J. Electron. Test., 2005)

Graph-based simulation of quantum computation in the density matrix representation. - George F. Viamontes; Igor L. Markov; John P. Hayes (Quantum Inf. Comput., 2005)

Dependable communication synthesis for distributed embedded systems. - Nagarajan Kandasamy; John P. Hayes; Brian T. Murray (Reliab. Eng. Syst. Saf., 2005)

Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. - Amit Chowdhary; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. - Nagarajan Kandasamy; John P. Hayes; Brian T. Murray (IEEE Trans. Parallel Distributed Syst., 2005)

On-Chip Test Generation Using Linear Subspaces. - Ramashis Das; Igor L. Markov; John P. Hayes (ETS, 2006)

A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. - Jia-Yi Chen; Michael P. Flynn; John P. Hayes (ISSCC, 2006)

Data structures and algorithms for simplifying reversible circuits. - Aditya K. Prasad; Vivek V. Shende; Igor L. Markov; John P. Hayes; Ketan N. Patel (ACM J. Emerg. Technol. Comput. Syst., 2006)

Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. - Feng Gao 017; John P. Hayes (J. Low Power Electron., 2006)

Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. - Feng Gao 017; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

High-level delay test generation for modular circuits. - Joonhwan Yi; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Monitoring Transient Errors in Sequential Circuits. - Ramashis Das; John P. Hayes (ATS, 2007)

Enhancing design robustness with reliability-aware resynthesis and logic simulation. - Smita Krishnaswamy; Stephen Plaza; Igor L. Markov; John P. Hayes (ICCAD, 2007)

Checking equivalence of quantum circuits and states. - George F. Viamontes; Igor L. Markov; John P. Hayes (ICCAD, 2007)

Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks. - Sungsoon Cho; John P. Hayes (LCN, 2007)

An Analysis Framework for Transient-Error Tolerance. - John P. Hayes; Ilia Polian; Bernd Becker 001 (VTS, 2007)

Tracking Uncertainty with Probabilistic Logic Circuit Testing. - Smita Krishnaswamy; Igor L. Markov; John P. Hayes (IEEE Des. Test Comput., 2007)

A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. - Jia-Yi Chen; Michael P. Flynn; John P. Hayes (IEEE J. Solid State Circuits, 2007)

On the role of timing masking in reliable logic circuit design. - Smita Krishnaswamy; Igor L. Markov; John P. Hayes (DAC, 2008)

High-level vulnerability over space and time to insidious soft errors. - Kenneth M. Zick; John P. Hayes (HLDVT, 2008)

Optimizing router locations for minimum-energy wireless networks. - Sungsoon Cho; John P. Hayes (LCN, 2008)

Optimal synthesis of linear reversible circuits. - Ketan N. Patel; Igor L. Markov; John P. Hayes (Quantum Inf. Comput., 2008)

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. - Smita Krishnaswamy; George F. Viamontes; Igor L. Markov; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2008)

Quantum Circuit Simulation. - George F. Viamontes; Igor L. Markov; John P. Hayes (Springer, 2009)

Improving testability and soft-error resilience through retiming. - Smita Krishnaswamy; Igor L. Markov; John P. Hayes (DAC, 2009)

Contactless testing: Possibility or pipe-dream? - Erik Jan Marinissen; Dae Young Lee; John P. Hayes; Chris Sellathamby; Brian Moore 001; Steven Slupsky; Laurence Pujol (DATE, 2009)

On-line characterization and reconfiguration for single event upset variations. - Kenneth M. Zick; John P. Hayes (IOLTS, 2009)

Signature-Based SER Analysis and Design of Logic Circuits. - Smita Krishnaswamy; Stephen Plaza; Igor L. Markov; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Advanced modeling of faults in Reversible circuits. - Ilia Polian; John P. Hayes (EWDTS, 2010)

On-line sensing for healthier FPGA systems. - Kenneth M. Zick; John P. Hayes (FPGA, 2010)

Self-Test and Adaptation for Random Variations in Reliability. - Kenneth M. Zick; John P. Hayes (FPL, 2010)

Toward Physically-Adaptive Computing. - Kenneth M. Zick; John P. Hayes (SASO, 2010)

Scalable and accurate estimation of probabilistic behavior in sequential circuits. - Chien-Chih Yu; John P. Hayes (VTS, 2010)

A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits. - Dae Young Lee; David D. Wentzloff; John P. Hayes (A-SSCC, 2011)

Trigonometric method to handle realistic error probabilities in logic circuits. - Chien-Chih Yu; John P. Hayes (DATE, 2011)

Wireless wafer-level testing of integrated circuits via capacitively-coupled channels. - Dae Young Lee; David D. Wentzloff; John P. Hayes (DDECS, 2011)

Tomographic Testing and Validation of Probabilistic Circuits. - Alexandru Paler; Armin Alaghi; Ilia Polian; John P. Hayes (ETS, 2011)

Selective Hardening: Toward Cost-Effective Error Tolerance. - Ilia Polian; John P. Hayes (IEEE Des. Test Comput., 2011)

Modeling and Mitigating Transient Errors in Logic Circuits. - Ilia Polian; John P. Hayes; Sudhakar M. Reddy; Bernd Becker 001 (IEEE Trans. Dependable Secur. Comput., 2011)

Detection and diagnosis of faulty quantum circuits. - Alexandru Paler; Ilia Polian; John P. Hayes (ASP-DAC, 2012)

Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo. - Chien-Chih Yu; Armin Alaghi; John P. Hayes (ICCAD, 2012)

A spectral transform approach to stochastic circuits. - Armin Alaghi; John P. Hayes (ICCD, 2012)

Robust Coupling Delay Test Sets. - Joonhwan Yi; John P. Hayes (J. Electron. Test., 2012)

Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems. - Kenneth M. Zick; John P. Hayes (ACM Trans. Reconfigurable Technol. Syst., 2012)

Stochastic circuits for real-time image-processing applications. - Armin Alaghi; Cheng Li; John P. Hayes (DAC, 2013)

Design of stochastic Viterbi decoders for convolutional codes. - Te-Hsuan Chen; John P. Hayes (DDECS, 2013)

Approximate simulation of circuits with probabilistic behavior. - Alexandru Paler; Josef Kinseher; Ilia Polian; John P. Hayes (DFTS, 2013)

Exploiting correlation in stochastic circuit design. - Armin Alaghi; John P. Hayes (ICCD, 2013)

Survey of Stochastic Computing. - Armin Alaghi; John P. Hayes (ACM Trans. Embed. Comput. Syst., 2013)

Design, Analysis and Test of Logic Circuits Under Uncertainty - Smita Krishnaswamy; Igor L. Markov; John P. Hayes (Springer, 2013)

Fast and accurate computation using stochastic circuits. - Armin Alaghi; John P. Hayes (DATE, 2014)

Stochastic Logic Realization of Matrix Operations. - Pai-Shun Ting; John Patrick Hayes (DSD, 2014)

Analyzing and controlling accuracy in stochastic circuits. - Te-Hsuan Chen; John P. Hayes (ICCD, 2014)

Behavior of stochastic circuits under severe error conditions. - Te-Hsuan Chen; Armin Alaghi; John P. Hayes (it Inf. Technol., 2014)

Equivalence among stochastic logic circuits and its application. - Te-Hsuan Chen; John P. Hayes (DAC, 2015)

Introduction to stochastic computing and its challenges. - John P. Hayes (DAC, 2015)

Low-Area and High-Speed Approximate Matrix-Vector Multiplier. - I-Che Chen; John P. Hayes (DDECS, 2015)

On the Functions Realized by Stochastic Computing Circuits. - Armin Alaghi; John P. Hayes (ACM Great Lakes Symposium on VLSI, 2015)

Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. - Armin Alaghi; Wei-Ting Jonas Chan; John P. Hayes; Andrew B. Kahng; Jiajia Li 002 (ICCAD, 2015)

Dimension reduction in statistical simulation of digital circuits. - Armin Alaghi; John P. Hayes (SpringSim (TMS-DEVS), 2015)

STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis. - Armin Alaghi; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Isolation-based decorrelation of stochastic circuits. - Pai-Shun Ting; John P. Hayes (ICCD, 2016)

Design of Division Circuits for Stochastic Computing. - Te-Hsuan Chen; John P. Hayes (ISVLSI, 2016)

Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. - Vincent T. Lee; Armin Alaghi; John P. Hayes; Visvesh Sathe 001; Luis Ceze (DATE, 2017)

Eliminating a hidden error source in stochastic circuits. - Pai-Shun Ting; John P. Hayes (DFT, 2017)

Building a Better Random Number Generator for Stochastic Computing. - Florian Neugebauer; Ilia Polian; John P. Hayes (DSD, 2017)

Achieving progressive precision in stochastic computing. - Te-Hsuan Chen; Pai-Shun Ting; John P. Hayes (GlobalSIP, 2017)

On the Role of Sequential Circuits in Stochastic Computing. - Pai-Shun Ting; John P. Hayes (ACM Great Lakes Symposium on VLSI, 2017)

Design of accurate stochastic number generators with noisy emerging devices for stochastic computing. - Meng Yang; John P. Hayes; Deliang Fan; Weikang Qian (ICCAD, 2017)

Trading Accuracy for Energy in Stochastic Circuit Design. - Armin Alaghi; Wei-Ting Jonas Chan; John P. Hayes; Andrew B. Kahng; Jiajia Li 002 (ACM J. Emerg. Technol. Comput. Syst., 2017)

Maxflow: Minimizing Latency in Hybrid Stochastic-Binary Systems. - Pai-Shun Ting; John P. Hayes (ACM Great Lakes Symposium on VLSI, 2018)

A comparison of perspectives of Kuwaiti and Indonesian residents towards e-government. - Dinesh A. Mirchandani; Yunus Kathawala; Julius H. Johnson Jr.; John P. Hayes; Sudhir Chawla (Electron. Gov. an Int. J., 2018)

Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. - Florian Neugebauer; Ilia Polian; John P. Hayes (ACM J. Emerg. Technol. Comput. Syst., 2018)

S-box-based random number generation for stochastic computing. - Florian Neugebauer; Ilia Polian; John P. Hayes (Microprocess. Microsystems, 2018)

The Promise and Challenge of Stochastic Computing. - Armin Alaghi; Weikang Qian; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

On the maximum function in stochastic computing. - Florian Neugebauer; Ilia Polian; John P. Hayes (CF, 2019)

Exploiting Randomness in Stochastic Computing. - Pai-Shun Ting; John P. Hayes (ICCAD, 2019)

On the Limits of Stochastic Computing. - Florian Neugebauer; Ilia Polian; John P. Hayes (ICRC, 2019)

Impact of Autocorrelation on Stochastic Circuit Accuracy. - Timothy J. Baker; John P. Hayes (ISVLSI, 2019)

Removing constant-induced errors in stochastic circuits. - Pai-Shun Ting; John P. Hayes (IET Comput. Digit. Tech., 2019)

Equivalence Among Stochastic Logic Circuits and its Application to Synthesis. - Te-Hsuan Chen; John P. Hayes (IEEE Trans. Emerg. Top. Comput., 2019)

The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing. - Timothy J. Baker; John P. Hayes (DATE, 2020)

Bayesian Accuracy Analysis of Stochastic Circuits. - Timothy J. Baker; John P. Hayes (ICCAD, 2020)

Exploring Target Function Approximation for Stochastic Circuit Minimization. - Chen Wang 072; Weihua Xiao; John P. Hayes; Weikang Qian (ICCAD, 2020)

Hardware-based Fast Real-time Image Classification with Stochastic Computing. - Ponnanna Kelettira Muthappa; Florian Neugebauer; Ilia Polian; John P. Hayes (ICCD, 2020)

Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. - Junseok Oh; Florian Neugebauer; Ilia Polian; John P. Hayes (ISVLSI, 2020)

Benefits of Stochastic Computing in Hearing Aid Filterbank Design. - Timothy J. Baker; Yiqiu Sun 002; John P. Hayes (BioCAS, 2021)

Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications. - Ilia Polian; John P. Hayes; Vincent T. Lee; Weikang Qian (IEEE Des. Test, 2021)

Analyzing Multilevel Stochastic Circuits using Correlation Matrices. - Owen Hoffend; John P. Hayes (DDECS, 2022)

Stochastic Computing Architectures for Lightweight LSTM Neural Networks. - Roshwin Sengupta; Ilia Polian; John P. Hayes (DDECS, 2022)

Wavelet Transform Assisted Neural Networks for Human Activity Recognition. - Roshwin Sengupta; Ilia Polian; John P. Hayes (ISCAS, 2022)

Multiplexer-Majority Chains: Managing Correlation and Cost in Stochastic Number Generation. - Timothy J. Baker; Owen Hoffend; John P. Hayes (NANOARCH, 2022)

CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design. - Timothy J. Baker; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2022)

Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior. - Timothy J. Baker; John P. Hayes (DATE, 2023)

Stochastic Computing as a Defence Against Adversarial Attacks. - Florian Neugebauer; Vivek Vekariya; Ilia Polian; John P. Hayes (DSN-W, 2023)

Mitigating the Correlation Problem in Multi-Layer Stochastic Circuits. - Owen Hoffend; John P. Hayes (ICRC, 2023)

Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks. - Roshwin Sengupta; Ilia Polian; John P. Hayes (ATS, 2024)

Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design. - Roshwin Sengupta; Ilia Polian; John P. Hayes (DDECS, 2024)

Low-Power Continuous Wavelet Transform Employing Stochastic Computing. - Roshwin Sengupta; Ilia Polian; John P. Hayes (ISCAS, 2025)