Fault Tolerance of a Class of Connecting Networks. - John Paul Shen; John P. Hayes (ISCA, 1980)

Fault tolerance analysis of several interconnection networks. - John Paul Shen (ICPP, 1982)

The design of two easily-testable VLSI array multipliers. - F. Joel Ferguson; John Paul Shen (IEEE Symposium on Computer Arithmetic, 1983)

Easily-Testable (N, K) Shuffle/Exchange Networks. - David C. H. Lee; John Paul Shen (ICPP, 1983)

On-Line Self-Monitoring Using Signatured Instruction Streams. - Michael A. Schuette; John Paul Shen (ITC, 1983)

Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. - Wojciech Maly; F. Joel Ferguson; John Paul Shen (ITC, 1984)

The Design of Easily Tastabel VLSI Array Multipliers. - John Paul Shen; F. Joel Ferguson (IEEE Trans. Computers, 1984)

Fault-Tolerance of Dynamic-Full-Access Interconnection Networks. - John Paul Shen; John P. Hayes (IEEE Trans. Computers, 1984)

Automated Design for Testability of Semicustom Integrated Circuits. - Patrick P. Fasang; Michael A. Schuette; John Paul Shen; William A. Gwaltney (ITC, 1985)

Inductive Fault Analysis of MOS Integrated Circuits. - John Paul Shen; Wojciech Maly; F. Joel Ferguson (IEEE Des. Test, 1985)

Highlights of CMU Research on CAD, CAM, CAT of VLSI Circuits. - John Paul Shen (FJCC, 1986)

Fault-tolerance and performance analysis of beta-networks. - John Paul Shen; John P. Hayes; Luigi Ciminiera; Angelo Serra (Parallel Comput., 1986)

Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks. - Ronald P. Bianchini Jr.; John Paul Shen (IEEE Trans. Computers, 1987)

Processor Control Flow Monitoring Using Signatured Instruction Streams. - Michael A. Schuette; John Paul Shen (IEEE Trans. Computers, 1987)

The White Dwarf: A High-Performance Application-Specific Processor. - Andrew Wolfe; Maurício Breternitz Jr.; Chriss Stephens; A. L. Ting; David Blair Kirk; Ronald P. Bianchini Jr.; John Paul Shen (ISCA, 1988)

Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. - John Paul Shen; F. Joel Ferguson (ITC, 1988)

Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors. - Kent D. Wilken; John Paul Shen (ITC, 1988)

Organization of array data for concurrent memory access. - Maurício Breternitz Jr.; John Paul Shen (MICRO, 1988)

Flexible processors: a promising application-specific processor design approach. - Andrew Wolfe; John Paul Shen (MICRO, 1988)

A CMOS fault extractor for inductive fault analysis. - F. Joel Ferguson; John Paul Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Architecture Synthesis of High-Performance Application-Specific Processors. - Maurício Breternitz Jr.; John Paul Shen (DAC, 1990)

Evaluation and Synthesis of Self-Monitoring State Machines. - Scott H. Robinson; John Paul Shen (ICCAD, 1990)

Continuous signature monitoring: low-cost concurrent detection of processor control errors. - Kent D. Wilken; John Paul Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A Variable Instruction Stream Extension to the VLIW Architecture. - Andrew Wolfe; John Paul Shen (ASPLOS, 1991)

Exploiting Instruction-Level Resource Parallelism for Transparent, Integrated Control-Flow Monitoring. - Michael A. Schuette; John Paul Shen (FTCS, 1991)

Instruction Level Profiling and Evaluation of the IBM/6000. - Chriss Stephens; Bryce Cogswell; John Heinlein; Gregory Palmer; John Paul Shen (ISCA, 1991)

Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. - Maurício Breternitz Jr.; John Paul Shen (MICRO, 1991)

An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. - Michael A. Schuette; John Paul Shen (MICRO, 1991)

Direct Methods for Synthesis of Self-Monitoring State Machines. - Scott H. Robinson; John Paul Shen (FTCS, 1992)

Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. - Trung A. Diep; Mikko H. Lipasti; John Paul Shen (ICCD, 1993)

Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture. - Chris J. Newburn; Andrew S. Huang; John Paul Shen (Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993)

EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. - Trung A. Diep; John Paul Shen; Mike Phillip (MICRO, 1993)

Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer. - Michael A. Schuette; John Paul Shen (J. Supercomput., 1993)

A PDG-based Tool and its Use in Analyzing Program Control Dependences. - Chris J. Newburn; Derek B. Noonburg; John Paul Shen (IFIP PACT, 1994)

Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. - Andrew S. Huang; Gert Slavenburg; John Paul Shen (ISCA, 1994)

Theoretical modeling of superscalar processor performance. - Derek B. Noonburg; John Paul Shen (MICRO, 1994)

Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring. - Michael A. Schuette; John Paul Shen (IEEE Trans. Computers, 1994)

Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures. - Trung A. Diep; John Paul Shen (FTCS, 1995)

Performance Evaluation of the PowerPC 620 Microarchitecture. - Trung A. Diep; Christopher Nelson; John Paul Shen (ISCA, 1995)

A limit study of local memory requirements using value reuse profiles. - Andrew S. Huang; John Paul Shen (MICRO, 1995)

VMW: A Visualization-Based Microarchitecture Workbench. - Trung A. Diep; John Paul Shen (Computer, 1995)

Automatic partitioning of signal processing programs for symmetric multiprocessors. - Chris J. Newburn; John Paul Shen (IEEE PACT, 1996)

The Intrinsic Bandwidth Requirements of Ordinary Programs. - Andrew S. Huang; John Paul Shen (ASPLOS, 1996)

Value Locality and Load Value Prediction. - Mikko H. Lipasti; Christopher B. Wilkerson; John Paul Shen (ASPLOS, 1996)

Can Trace-Driven Simulators Accurately Predict Superscalar Performance? - Bryan Black; Andrew S. Huang; Mikko H. Lipasti; John Paul Shen (ICCD, 1996)

Exceeding the Dataflow Limit via Value Prediction. - Mikko H. Lipasti; John Paul Shen (MICRO, 1996)

A Realistic Study on Multithreaded Superscalar Processor Design. - Yuan C. Chou; Daniel P. Siewiorek; John Paul Shen (Euro-Par, 1997)

The Performance Potential of Value and Dependence Prediction. - Mikko H. Lipasti; John Paul Shen (Euro-Par, 1997)

A Framework for Statistical Modeling of Superscalar Processor Performance. - Derek B. Noonburg; John Paul Shen (HPCA, 1997)

Compiler Support for Low-Cost Synchronization Among Threads. - Chris J. Newburn; John Paul Shen (PARCO, 1997)

Superspeculative Microarchitecture for Beyond AD 2000. - Mikko H. Lipasti; John Paul Shen (Computer, 1997)

Post-pass partitioning of signal processing programs. - Chris J. Newburn; John Paul Shen (Int. J. Parallel Program., 1997)

Efficacy and Performance Impact of Value Prediction. - Bohuslav Rychlik; John Faistl; Bryon Krug; John Paul Shen (IEEE PACT, 1998)

Hardware to Software Migration with Real-Time Thread Integration. - Alexander G. Dean; John Paul Shen (EUROMICRO, 1998)

Load Execution Latency Reduction. - Bryan Black; Brian Mueller; Stephanie Postal; Ryan N. Rakvic; Noppanunt Utamaphethai; John Paul Shen (International Conference on Supercomputing, 1998)

Techniques for Software Thread Integration in Real-Time Embedded Systems. - Alexander G. Dean; John Paul Shen (RTSS, 1998)

Calibration of Microprocessor Performance Models. - Bryan Black; John Paul Shen (Computer, 1998)

Exploiting Value Locality to Exceed the Dataflow Limit. - Mikko H. Lipasti; John Paul Shen (Int. J. Parallel Program., 1998)

Mispredicted Path Cache Effects. - Jonathan Combs; Candice Bechem Combs; John Paul Shen (Euro-Par, 1999)

Reducing branch misprediction penalties via dynamic control independence detection. - Yuan C. Chou; Jason Fung; John Paul Shen (International Conference on Supercomputing, 1999)

The Block-Based Trace Cache. - Bryan Black; Bohuslav Rychlik; John Paul Shen (ISCA, 1999)

System-Level Issues for Software Thread Integration: Guest Triggering and Host Selection. - Alexander G. Dean; John Paul Shen (RTSS, 1999)

Superscalar Processor Validation at the Microarchitecture Level. - Noppanunt Utamaphethai; R. D. (Shawn) Blanton; John Paul Shen (VLSI Design, 1999)

An integrated functional performance simulator. - Candice Bechem; Jonathan Combs; Noppanunt Utamaphethai; Bryan Black; R. D. (Shawn) Blanton; John Paul Shen (IEEE Micro, 1999)

Instruction path coprocessors. - Yuan C. Chou; John Paul Shen (ISCA, 2000)

Completion time multiple branch prediction for enhancing trace cache performance. - Ryan N. Rakvic; Bryan Black; John Paul Shen (ISCA, 2000)

PipeRench implementation of the instruction path coprocessor. - Yuan C. Chou; Pazhani Pillai; Herman Schmit; John Paul Shen (MICRO, 2000)

Effectiveness of Microarchitecture Test Program Generation. - Noppanunt Utamaphethai; R. D. (Shawn) Blanton; John Paul Shen (IEEE Des. Test Comput., 2000)

A Buffer-Oriented Methodology for Microarchitecture Validation. - Noppanunt Utamaphethai; R. D. (Shawn) Blanton; John Paul Shen (J. Electron. Test., 2000)

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. - Noppanunt Utamaphethai; Ronald D. Blanton; John Paul Shen (HLDVT, 2001)

Register Renaming and Scheduling for Dynamic Execution of Predicated Code. - Perry H. Wang; Hong Wang 003; Ralph-Michael Kling; Kalpana Ramakrishnan; John Paul Shen (HPCA, 2001)

Parallel Cachelets. - Deepak Limaye; Ryan N. Rakvic; John Paul Shen (ICCD, 2001)

Clear and Present Tensions in Microprocessor Design. - John Paul Shen (ICCD, 2001)

Speculative precomputation: long-range prefetching of delinquent loads. - Jamison D. Collins; Hong Wang 003; Dean M. Tullsen; Christopher J. Hughes; Yong-Fong Lee; Daniel M. Lavery; John Paul Shen (ISCA, 2001)

Dynamic speculative precomputation. - Jamison D. Collins; Dean M. Tullsen; Hong Wang 003; John Paul Shen (MICRO, 2001)

Coming challenges in microarchitecture and architecture. - Ronny Ronen; Avi Mendelson; Konrad Lai; Shih-Lien Lu; Fred J. Pollack; John Paul Shen (Proc. IEEE, 2001)

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. - R. David Weldon; Steven S. Chang; Hong Wang 003; Gerolf Hoflehner; Perry H. Wang; Daniel M. Lavery; John Paul Shen (Interaction between Compilers and Computer Architectures, 2002)

Non-Vital Loads. - Ryan N. Rakvic; Bryan Black; Deepak Limaye; John Paul Shen (HPCA, 2002)

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. - Perry H. Wang; Hong Wang 003; Jamison D. Collins; Ed Grochowski; Ralph-Michael Kling; John Paul Shen (HPCA, 2002)

Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. - Murali Annavaram; Trung A. Diep; John Paul Shen (ICCD, 2002)

Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. - Shih-Wei Liao; Perry H. Wang; Hong Wang 003; John Paul Shen; Gerolf Hoflehner; Daniel M. Lavery (PLDI, 2002)

Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. - Richard A. Hankins; Trung A. Diep; Murali Annavaram; Brian Hirano; Harald Eri; Hubert Nueckel; John Paul Shen (MICRO, 2003)

A framework for modeling and optimization of prescient instruction prefetch. - Tor M. Aamodt; Pedro Marcuello; Paul Chow; Antonio González 001; Per Hammarlund; Hong Wang 003; John Paul Shen (SIGMETRICS, 2003)

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (ASPLOS, 2004)

Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. - Dongkeun Kim; Shih-Wei Liao; Perry H. Wang; Juan del Cuvillo; Xinmin Tian; Xiang Zou; Hong Wang 003; Donald Yeung; Milind Girkar; John Paul Shen (CGO, 2004)

Hardware Support for Prescient Instruction Prefetch. - Tor M. Aamodt; Paul Chow; Per Hammarlund; Hong Wang 003; John Paul Shen (HPCA, 2004)

Best of Both Latency and Throughput. - Ed Grochowski; Ronny Ronen; John Paul Shen; Hong Wang 003 (ICCD, 2004)

Helper Threads via Virtual Multithreading. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (IEEE Micro, 2004)

A case for shared instruction cache on chip multiprocessors running OLTP. - Partha Kundu; Murali Annavaram; Trung A. Diep; John Paul Shen (SIGARCH Comput. Archit. News, 2004)

A Dependency Chain Clustered Microarchitecture. - Satish Narayanasamy; Hong Wang 003; Perry H. Wang; John Paul Shen; Brad Calder (IPDPS, 2005)

Mitigating Amdahl's Law through EPI Throttling. - Murali Annavaram; Ed Grochowski; John Paul Shen (ISCA, 2005)

Multiple Instruction Stream Processor. - Richard A. Hankins; Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Ryan N. Rakvic; Hong Wang 003; John Paul Shen (ISCA, 2006)

Die Stacking (3D) Microarchitecture. - Bryan Black; Murali Annavaram; Ned Brekelbaum; John DeVale; Lei Jiang; Gabriel H. Loh; Don McCaule; Patrick Morrow; Donald W. Nelson; Daniel Pantuso; Paul Reed; Jeff Rupley; et al. (MICRO, 2006)

Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. - Carlos Madriles; Carlos García Quiñones; F. Jesús Sánchez; Pedro Marcuello; Antonio González 001; Dean M. Tullsen; Hong Wang 003; John Paul Shen (IEEE Trans. Parallel Distributed Syst., 2008)

Space-Time Graph Modeling of Ride Requests Based on Real-World Data. - Abhinav Jauhri; Brian Foo; Jérôme Berclaz; Chih Chi Hu; Radek Grzeszczuk; Vasu Parameswaran; John Paul Shen (AAAI Workshops, 2017)

Data Driven Analysis of the Potentials of Dynamic Ride Pooling. - Min Hao Chen; Abhinav Jauhri; John Paul Shen (IWCTS@SIGSPATIAL, 2017)

SurfaceVibe: vibration-based tap & swipe tracking on ubiquitous surfaces. - Shijia Pan; Ceferino Gabriel Ramirez; Mostafa Mirshekari; Jonathon Fagert; Albert Jin Chung; Chih Chi Hu; John Paul Shen; Hae Young Noh; Pei Zhang 001 (IPSN, 2017)

On the Real-time Vehicle Placement Problem. - Abhinav Jauhri; Carlee Joe-Wong; John Paul Shen (CoRR, 2017)

Improving Bag-Of-Words: Capturing Local Information for Motion-Based Activity Recognition. - Ming Zeng 009; Tong Yu 001; Ole J. Mengshoel; Helen Qin; Chris Lee; John Paul Shen (UbiComp/ISWC Adjunct, 2018)

Audio-visual TED corpus: enhancing the TED-LIUM corpus with facial information, contextual text and object recognition. - Guan-Lin Chao; Chih Chi Hu; Bing Liu 024; John Paul Shen; Ian R. Lane (UbiComp/ISWC Adjunct, 2019)

AttriNet: learning mid-level features for human activity recognition with deep belief networks. - Harideep Nair; Cathy Tan; Ming Zeng 009; Ole J. Mengshoel; John Paul Shen (UbiComp/ISWC Adjunct, 2019)

Deep Speaker Embedding for Speaker-Targeted Automatic Speech Recognition. - Guan-Lin Chao; John Paul Shen; Ian R. Lane (NLPIR, 2019)

Sky Segmentation for Enhanced Depth Reconstruction and Bokeh Rendering with Efficient Architectures. - Tyler Nuanes; Matt Elsey; Radek Grzeszczuk; John Paul Shen (Computational Imaging, 2020)

Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing. - Harideep Nair; John Paul Shen; James E. Smith 001 (CoRR, 2020)

Generating Realistic Ride-Hailing Datasets Using GANs. - Abhinav Jauhri; Brad Stocks; Jian-Hui Li; Koichi Yamada; John Paul Shen (ACM Trans. Spatial Algorithms Syst., 2020)

Unsupervised Clustering of Time Series Signals Using Neuromorphic Energy-Efficient Temporal Neural Networks. - Shreyas Chaudhari; Harideep Nair; José M. F. Moura; John Paul Shen (ICASSP, 2021)

A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. - Harideep Nair; John Paul Shen; James E. Smith 001 (ISVLSI, 2021)

TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. - Harideep Nair; Prabhu Vellaisamy; Santha Bhasuthkar; John Paul Shen (ISVLSI, 2022)

Towards a Design Framework for TNN-Based Neuromorphic Sensory Processing Units. - Prabhu Vellaisamy; John Paul Shen (CoRR, 2022)

SemNet: Learning semantic attributes for human activity recognition with deep belief networks. - Shanmuga Venkatachalam; Harideep Nair; Ming Zeng 009; Cathy Tan; Ole J. Mengshoel; John Paul Shen (Frontiers Big Data, 2022)

tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI. - Harideep Nair; Prabhu Vellaisamy; Albert Chen 002; Joseph Finn; Anna Li; Manav Trivedi; John Paul Shen (ISCAS, 2023)

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. - Prabhu Vellaisamy; Harideep Nair; Joseph Finn; Manav Trivedi; Albert Chen 002; Anna Li; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (ISVLSI, 2023)

IDIoT: Multimodal Framework for Ubiquitous Identification and Assignment of Human-carried Wearable Devices. - Adeola Bannis; Shijia Pan; Carlos Ruiz Dominguez; John Paul Shen; Hae Young Noh; Pei Zhang 001 (ACM Trans. Internet Things, 2023)

TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning. - Harideep Nair; David Barajas-Jasso; Quinn Jacobson; John Paul Shen (AICAS, 2024)

Realtime Person Identification via Gait Analysis Using IMU Sensors on Edge Devices. - Shanmuga Venkatachalam; Harideep Nair; Prabhu Vellaisamy; Yongqi Zhou; Ziad Youssfi; John Paul Shen (ICONS, 2024)

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. - Prabhu Vellaisamy; Harideep Nair; Di Wu; R. D. Shawn Blanton; John Paul Shen (ISVLSI, 2024)

NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors. - Harideep Nair; William Leyman; Agastya Sampath; Quinn Jacobson; John Paul Shen (NICE, 2024)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (VLSI-SoC, 2024)

OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (CoRR, 2024)

Realtime Person Identification via Gait Analysis. - Shanmuga Venkatachalam; Harideep Nair; Prabhu Vellaisamy; Yongqi Zhou; Ziad Youssfi; John Paul Shen (CoRR, 2024)

Corrigendum: SemNet: Learning semantic attributes for human activity recognition with deep belief networks. - Shanmuga Venkatachalam; Harideep Nair; Ming Zeng 009; Cathy Tan; Ole J. Mengshoel; John Paul Shen (Frontiers Big Data, 2024)

TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering. - Prabhu Vellaisamy; Harideep Nair; Vamsikrishna Ratnakaram; Dhruv Gupta; John Paul Shen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. - Prabhu Vellaisamy; Harideep Nair; Thomas Kang; Yichen Ni; Haoyang Fan; Bin Qi; Jeff Chen; R. D. Shawn Blanton; John Paul Shen (DATE, 2025)

Characterizing and Optimizing LLM Inference Workloads on CPU-GPU Coupled Architectures. - Prabhu Vellaisamy; Thomas Labonte; Sourav Chakraborty 007; Matt Turner; Samantika Sury; John Paul Shen (CoRR, 2025)