A vertically integrated VLSI design environment. - Jonathan B. Rosenberg; David G. Boyer; John A. Dallen; Stephen W. Daniel; Charles J. Poirier; John Poulton; C. Durward Rogers; Neil Weste (DAC, 1983)

Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes. - Henry Fuchs; Jack Goldfeather; Jeff P. Hultquist; Susan Spach; John D. Austin; Frederick P. Brooks Jr.; John G. Eyles; John Poulton (Advances in Computer Graphics, 1985)

Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes. - Henry Fuchs; Jack Goldfeather; Jeff P. Hultquist; Susan Spach; John D. Austin; Frederick P. Brooks Jr.; John G. Eyles; John Poulton (SIGGRAPH, 1985)

Pixel-Planes 4: A Summary. - John G. Eyles; John D. Austin; Henry Fuchs; Trey Greer; John Poulton (Advances in Computer Graphics Hardware, 1987)

Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories. - Henry Fuchs; John Poulton; John G. Eyles; Trey Greer; Jack Goldfeather; David A. Ellsworth; Steven Molnar; Greg Turk; Brice Tebbs; Laura Israel (SIGGRAPH, 1989)

PixelFlow: high-speed rendering using image composition. - Steven Molnar; John G. Eyles; John Poulton (SIGGRAPH, 1992)

Breaking the frame-buffer bottleneck with logic-enhanced memories. - John Poulton; John G. Eyles; Steven E. Molnar; Henry Fuchs (IEEE Computer Graphics and Applications, 1992)

An Embedded DRAM for CMOS ASICs. - John Poulton (ARVLSI, 1997)

PixelFlow: The Realization. - John G. Eyles; Steven Molnar; John Poulton; Trey Greer; Anselmo Lastra; Nick England; Lee Westover (Workshop on Graphics Hardware, 1997)

Transmitter equalization for 4-Gbps signaling. - William J. Dally; John W. Poulton (IEEE Micro, 1997)

A tracking clock recovery receiver for 4-Gbps signaling. - John Poulton; William J. Dally; Steve Tell (IEEE Micro, 1998)

Problems and Prospects for Electrical Signaling. - John Poulton (ARVLSI, 1999)

Digital systems engineering. - William J. Dally; John W. Poulton (Cambridge University Press, 2001)

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. - Ramin Farjad-Rad; William J. Dally; Hiok-Tiaq Ng; Ramesh Senthinathan; Ming-Ju Edward Lee; Rohit Rathi; John Poulton (IEEE J. Solid State Circuits, 2002)

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. - Hiok-Tiaq Ng; Ming-Ju Edward Lee; Ramin Farjad-Rad; Ramesh Senthinathan; William J. Dally; Anhtuyet Nguyen; Rohit Rathi; Trey Greer; John Poulton; John H. Edmondson; James Tran (CICC, 2003)

CMOS High-Speed I/Os - Present and Future. - Ming-Ju Edward Lee; William J. Dally; Ramin Farjad-Rad; Hiok-Tiaq Ng; Ramesh Senthinathan; John H. Edmondson; John W. Poulton (ICCD, 2003)

Jitter transfer characteristics of delay-locked loops - theories and design techniques. - Ming-Ju Edward Lee; William J. Dally; Trey Greer; Hiok-Tiaq Ng; Ramin Farjad-Rad; John Poulton; Ramesh Senthinathan (IEEE J. Solid State Circuits, 2003)

A second-order semidigital clock recovery circuit based on injection locking. - Hiok-Tiaq Ng; Ramin Farjad-Rad; Ming-Ju Edward Lee; William J. Dally; Trey Greer; John Poulton; John H. Edmondson; Rohit Rathi; Ramesh Senthinathan (IEEE J. Solid State Circuits, 2003)

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. - Ramin Farjad-Rad; Anhtuyet Nguyen; James Tran; Trey Greer; John Poulton; William J. Dally; John H. Edmondson; Ramesh Senthinathan; Rohit Rathi; Ming-Ju Edward Lee; Hiok-Tiaq Ng (IEEE J. Solid State Circuits, 2004)

The design of DNA self-assembled computing circuitry. - Chris Dwyer; Leandra Vicci; John W. Poulton; Dorothy Erie; Richard Superfine; Sean Washburn; Russell M. Taylor II (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver. - Mike Yun He; John Poulton (IEEE J. Solid State Circuits, 2006)

A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications. - Robert Palmer; John Poulton; William J. Dally; John G. Eyles; Andrew M. Fuller; Trey Greer; Mark Horowitz; Mark Kellam; F. Quan; F. Zarkeshvari (ISSCC, 2007)

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. - John Poulton; Robert Palmer; Andrew M. Fuller; Trey Greer; John G. Eyles; William J. Dally; Mark Horowitz (IEEE J. Solid State Circuits, 2007)

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. - Brian S. Leibowitz; Robert Palmer; John Poulton; Yohan Frans; Simon Li; John M. Wilson 002; Michael Bucher; Andrew M. Fuller; John G. Eyles; Marko Aleksic; Trey Greer; Nhat Nguyen (IEEE J. Solid State Circuits, 2010)

A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. - John W. Poulton; William J. Dally; Xi Chen 033; John G. Eyles; Thomas H. Greer; Stephen G. Tell; C. Thomas Gray (ISSCC, 2013)

A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. - John W. Poulton; William J. Dally; Xi Chen 033; John G. Eyles; Thomas H. Greer; Stephen G. Tell; John M. Wilson 002; C. Thomas Gray (IEEE J. Solid State Circuits, 2013)

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. - Arijit Banerjee 002; Mahmut E. Sinangil; John W. Poulton; C. Thomas Gray; Benton H. Calhoun (ISQED, 2014)

8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. - John M. Wilson 002; Matthew R. Fojtik; John W. Poulton; Xi Chen 033; Stephen G. Tell; Thomas H. Greer; C. Thomas Gray; William J. Dally (ISSCC, 2016)

A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. - Mahmut E. Sinangil; John W. Poulton; Matthew R. Fojtik; Thomas H. Greer; Stephen G. Tell; Andreas J. Gotterba; Jesse Wang; Jason Golbus; Brian Zimmer; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2016)

A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors. - Arijit Banerjee 002; Ningxi Liu; Harsh N. Patel; Benton H. Calhoun; John W. Poulton; C. Thomas Gray (CICC, 2017)

A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers. - Laura Fick; Dennis Sylvester; John W. Poulton; John M. Wilson 002; C. Thomas Gray (ISCAS, 2017)

A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. - Sudhir S. Kudva; Sanquan Song; John W. Poulton; John M. Wilson 002; Wenxu Zhao; C. Thomas Gray (CICC, 2018)

Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. - Walker J. Turner; John W. Poulton; John M. Wilson 002; Xi Chen 033; Stephen G. Tell; Matthew Fojtik; Thomas H. Greer; Brian Zimmer; Sanquan Song; Nikola Nedovic; Sudhir S. Kudva; Sunil R. Sudhakaran; et al. (CICC, 2018)

A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. - John M. Wilson 002; Walker J. Turner; John W. Poulton; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (ISSCC, 2018)

Hardware-Enabled Artificial Intelligence. - William J. Dally; C. Thomas Gray; John Poulton; Brucek Khailany; John M. Wilson 002; Larry R. Dennison (VLSI Circuits, 2018)

Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. - Xi Chen 033; Sanquan Song; John Poulton; Nikola Nedovic; Brian Zimmer; Stephen G. Tell; C. Thomas Gray (CICC, 2019)

A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. - Sanquan Song; John Poulton; Xi Chen 033; Brian Zimmer; Stephen G. Tell; Walker J. Turner; Sudhir S. Kudva; Nikola Nedovic; John M. Wilson 002; C. Thomas Gray; William J. Dally (CICC, 2019)

A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. - John W. Poulton; John M. Wilson 002; Walker J. Turner; Brian Zimmer; Xi Chen 033; Sudhir S. Kudva; Sanquan Song; Stephen G. Tell; Nikola Nedovic; Wenxu Zhao; Sunil R. Sudhakaran; C. Thomas Gray; et al. (IEEE J. Solid State Circuits, 2019)

6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. - Xi Chen 033; Nikola Nedovic; Stephen G. Tell; Sudhir S. Kudva; Brian Zimmer; Thomas H. Greer; John W. Poulton; Sanquan Song; Walker J. Turner; John M. Wilson 002; C. Thomas Gray (ISSCC, 2020)

A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. - Yoshinori Nishi; John W. Poulton; Xi Chen 033; Sanquan Song; Brian Zimmer; Walker J. Turner; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (VLSI Technology and Circuits, 2022)

A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2023)

Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. - Walker J. Turner; John W. Poulton; Yoshinori Nishi; Xi Chen 033; Brian Zimmer; Sanquan Song; John M. Wilson 002; William J. Dally; C. Thomas Gray (CICC, 2024)

A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. - Yoshinori Nishi; John W. Poulton; Walker J. Turner; Xi Chen 033; Sanquan Song; Brian Zimmer; Stephen G. Tell; Nikola Nedovic; John M. Wilson 002; William J. Dally; C. Thomas Gray (IEEE J. Solid State Circuits, 2024)