Capacitance driven clock mesh synthesis to minimize skew and power dissipation. - John Reuben; V. Mohammed Zackriya; Salma Nashit; Harish M. Kittur (IEICE Electron. Express, 2013)

A novel clock generation algorithm for system-on-chip based on least common multiple. - John Reuben; Harish M. Kittur; Mohd Shoaib (Comput. Electr. Eng., 2014)

Low Power fractional-n frequency Divider with Improved Resolution. - V. Mohammed Zackriya; John Reuben; Ashim Harsh; Harish M. Kittur (J. Circuits Syst. Comput., 2014)

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits. - Kamineni Sumanth Kumar; John Reuben (J. Circuits Syst. Comput., 2016)

Memristive logic: A framework for evaluation and comparison. - John Reuben; Rotem Ben Hur; Nimrod Wald; Nishil Talati; Ameer Haj Ali; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (PATMOS, 2017)

A Taxonomy and Evaluation Framework for Memristive Logic. - John Reuben; Nishil Talati; Nimrod Wald; Rotem Ben Hur; Ameer Haj Ali; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (Handbook of Memristor Networks, 2019)

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. - John Reuben; Dietmar Fey (NORCAS, 2019)

A Parallel-friendly Majority Gate to Accelerate In-memory Computation. - John Reuben; Stefan Pechmann (ASAP, 2020)

Direct state transfer in MLC based memristive ReRAM devices for ternary computing. - Dietmar Fey; John Reuben (ECCTD, 2020)

Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic. - Dietmar Fey; John Reuben; Stefan Slesazeck (ICECS, 2021)

Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. - John Reuben; Dietmar Fey (ISVLSI, 2021)

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates. - John Reuben; Stefan Pechmann (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Inner Product Computation In-Memory Using Distributed Arithmetic. - Vijaya Lakshmi; Vikramkumar Pudi; John Reuben (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. - Vijaya Lakshmi; John Reuben; Vikramkumar Pudi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories. - John Reuben; Dietmar Fey; Stefan Slesazeck (MOCAST, 2023)

Hyper Dimensional Computing with Ferroelectric Tunneling Junctions. - Stefan Slesazeck; Suzanne Lancaster; John Reuben; Shima Hosseinzadeh; Dietmar Fey; Thomas Mikolajick (NANOARCH, 2023)

On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory. - John Reuben; Suzanne Lancaster; Dietmar Fey; Stefan Slesazeck (NorCAS, 2024)

In-Memory Implementation of an Approximate Adder With Reduced Latency and Error. - Vijaya Lakshmi; Vikramkumar Pudi; John Reuben (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)