The microarchitecture of the synergistic processor for a cell processor. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IEEE J. Solid State Circuits, 2006)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)

Cell Broadband Engine processor vault security architecture. - Kanna Shimizu; H. Peter Hofstee; John S. Liberty (IBM J. Res. Dev., 2007)

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. - Steven C. Chan; Phillip J. Restle; Thomas J. Bucelot; John S. Liberty; Stephen Weitzel; John M. Keaty; Brian K. Flachs; Richard Volant; Peter Kapusta; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2009)

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor. - John S. Liberty; Adrian Barrera; David W. Boerstler; Thomas B. Chadwick; Scott R. Cottier; H. Peter Hofstee; Julie A. Rosser; Marty L. Tsai (IBM J. Res. Dev., 2013)