Two-dimensional IC layout compaction based on topological design rule checking. - John Valainis; Sinan Kaptanoglu; Erwin Liu; Roberto Suaya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Nonlinear transformer model for circuit simulation. - John H. Chan; Andrei Vladimirescu; Xiao-Chun Gao; Peter Liebmann; John Valainis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)