A VLSI Approach to Sound Synthesis. - John Wawrzynek; Carver Mead; Tzu-Mu Lin; Hsui-Lin Liu; Lounette M. Dyer (ICMC, 1984)

VLSI Concurrent Computation for Music Synthesis. - John Wawrzynek (1987)

The Center for New Music and Audio Technologies. - David Wessel; Richard Felciano; Adrian Freed; John Wawrzynek (ICMC, 1989)

A Multimedia Digital Signal Processing Tutoring System. - Sam Pointer; John Wawrzynek; David Wessel (ICMC, 1990)

VLSI Parallel Processing for Musical Sound Synthesis. - John Wawrzynek; Thorsten von Eicken (ICMC, 1990)

Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. - David E. Culler; Anurag Sah; Klaus E. Schauser; Thorsten von Eicken; John Wawrzynek (ASPLOS, 1991)

A Two-Dimensional Topological Compactor With Octagonal Geometry. - Paul de Dood; John Wawrzynek; Erwin Liu; Roberto Suaya (DAC, 1991)

SPERT: a VLIW/SIMD microprocessor for artificial neural network computations. - Krste Asanovic; James Beck; Brian Kingsbury; Phil Kohn; Nelson Morgan; John Wawrzynek (ASAP, 1992)

Designing A Connectionist Network Supercomputer. - Krste Asanovic; James Beck; Jerry Feldman; Nelson Morgan; John Wawrzynek (Int. J. Neural Syst., 1993)

Silicon auditory processors as computer peripherals. - John Lazzaro; John Wawrzynek; Misha Mahowald; Massimo Sivilotti; Dave Gillespie (IEEE Trans. Neural Networks, 1993)

The design of a neuro-microprocessor. - John Wawrzynek; Krste Asanovic; Nelson Morgan (IEEE Trans. Neural Networks, 1993)

Using simulations of reduced precision arithmetic to design a neuro-microprocessor. - Krste Asanovic; Nelson Morgan; John Wawrzynek (J. VLSI Signal Process., 1993)

Systems technologies for silicon auditory models. - John Lazzaro; John Wawrzynek; Alan Kramer (IEEE Micro, 1994)

A multi-sender asynchronous extension to the AER protocol. - John Lazzaro; John Wawrzynek (ARVLSI, 1995)

Silicon Models for Auditory Scene Analysis. - John Lazzaro; John Wawrzynek (NIPS, 1995)

SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. - John Wawrzynek; Krste Asanovic; Brian Kingsbury; James Beck; David Johnson 001; Nelson Morgan (NIPS, 1995)

A Micropower Analog VLSI HMM State Decoder for Wordspotting. - John Lazzaro; John Wawrzynek; Richard Lippmann (NIPS, 1996)

Spert-II: A Vector Microprocessor System. - John Wawrzynek; Krste Asanovic; Brian Kingsbury; David Johnson 001; James Beck; Nelson Morgan (Computer, 1996)

Datapath-oriented FPGA mapping and placement for configurable computing. - Timothy J. Callahan; John Wawrzynek (FCCM, 1997)

Garp: a MIPS processor with a reconfigurable coprocessor. - John R. Hauser; John Wawrzynek (FCCM, 1997)

A micropower analog circuit implementation of hidden Markov model state decoding. - John Lazzaro; John Wawrzynek; Richard P. Lippmann (IEEE J. Solid State Circuits, 1997)

Object Oriented Circuit-Generators in Java. - Michael Chu; Nicholas Weaver; Kolja Sulimma; André DeHon; John Wawrzynek (FCCM, 1998)

Fast Module Mapping and Placement for Datapaths in FPGAs. - Timothy J. Callahan; Philip Chong; André DeHon; John Wawrzynek (FPGA, 1998)

Instruction-Level Parallelism for Reconfigurable Computing. - Timothy J. Callahan; John Wawrzynek (FPL, 1998)

Reconfigurable Computing: What, Why, and Implications for Design Automation. - André DeHon; John Wawrzynek (DAC, 1999)

HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. - William Tsu; Kip Macy; Atul Joshi; Randy Huang; Norman Walker; Tony Tung; Omid Rowhani; George Varghese; John Wawrzynek; André DeHon (FPGA, 1999)

A fixed-point recursive digital oscillator for additive synthesis of audio. - Todd D. Hodes; John R. Hauser; John Wawrzynek; Adrian Freed; David Wessel (ICASSP, 1999)

Real products, real technology Guest Editor's Introduction]. - Norman P. Jouppi; John Wawrzynek (IEEE Micro, 1999)

JPEG Quality Transcoding Using Neural Networks Trained With a Perceptual Error Measure. - John Lazzaro; John Wawrzynek (Neural Comput., 1999)

A Comparison of the AES Candidates Amenability to FPGA Implementation. - Nicholas Weaver; John Wawrzynek (AES Candidate Conference, 2000)

Adapting software pipelining for reconfigurable computing. - Timothy J. Callahan; John Wawrzynek (CASES, 2000)

Stream Computations Organized for Reconfigurable Execution (SCORE). - Eylon Caspi; Michael Chu; Randy Huang; Joseph Yeh; John Wawrzynek; André DeHon (FPL, 2000)

The Garp Architecture and C Compiler. - Timothy J. Callahan; John R. Hauser; John Wawrzynek (Computer, 2000)

A case for network musical performance. - John Lazzaro; John Wawrzynek (NOSSDAV, 2001)

Hardware-Assisted Fast Routing. - André DeHon; Randy Huang; John Wawrzynek (FCCM, 2002)

The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks. - Nicholas Weaver; John Wawrzynek (FCCM, 2002)

Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. - Yury Markovsky; Eylon Caspi; Randy Huang; Joseph Yeh; Michael Chu; John Wawrzynek; André DeHon (FPGA, 2002)

Stochastic, spatial routing for hypergraphs, trees, and meshes. - Randy Huang; John Wawrzynek; André DeHon (FPGA, 2003)

Post-placement C-slow retiming for the xilinx virtex FPGA. - Nicholas Weaver; Yury Markovsky; Yatish Patel; John Wawrzynek (FPGA, 2003)

Quality based compute-resource allocation in real-time signal processing. - Joseph Yeh; John Wawrzynek (ICASSP (2), 2003)

Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics. - John Wawrzynek; Keith Diefendorff (IEEE Micro, 2003)

The SFRA: a corner-turn FPGA architecture. - Nicholas Weaver; John R. Hauser; John Wawrzynek (FPGA, 2004)

The Design And Application Of A High-End Reconfigurable Computing System. - Chen Chang; John Wawrzynek; Pierre-Yves Droz; Robert W. Brodersen (ERSA, 2005)

Defect Tolerance in Multiple-FPGA Systems. - Zohair Hyder; John Wawrzynek (FPL, 2005)

BEE2: A High-End Reconfigurable Computing System. - Chen Chang; John Wawrzynek; Robert W. Brodersen (IEEE Des. Test Comput., 2005)

Research accelerator for multiple processors. - David A. Patterson 001; Arvind 001; Krste Asanovic; Derek Chiou; James C. Hoe; Christos Kozyrakis; Shih-Lien Lu; Mark Oskin; Jan M. Rabaey; John Wawrzynek (Hot Chips Symposium, 2006)

Stochastic spatial routing for reconfigurable networks. - André DeHon; Randy Huang; John Wawrzynek (Microprocess. Microsystems, 2006)

Stream computations organized for reconfigurable execution. - André DeHon; Yury Markovsky; Eylon Caspi; Michael Chu; Randy Huang; Stylianos Perissakis; Laura Pozzi 001; Joseph Yeh; John Wawrzynek (Microprocess. Microsystems, 2006)

An Implementation Guide for RTP MIDI. - John Lazzaro; John Wawrzynek (RFC, 2006)

RAMP Blue: A Message-Passing Manycore System in FPGAs. - Alex Krasnov; Andrew Schultz; John Wawrzynek; Greg Gibeling; Pierre-Yves Droz (FPL, 2007)

Adventures with a Reconfigurable Research Platform. - John Wawrzynek (FPL, 2007)

RAMP: Research Accelerator for Multiple Processors. - John Wawrzynek; David A. Patterson 001; Mark Oskin; Shih-Lien Lu; Christoforos E. Kozyrakis; James C. Hoe; Derek Chiou; Krste Asanovic (IEEE Micro, 2007)

Workloads of the Future. - Jan M. Rabaey; Daniel Burke; Ken Lutz; John Wawrzynek (IEEE Des. Test Comput., 2008)

Using adaptive routing to compensate for performance heterogeneity. - Yury Markovsky; Yatish Patel; John Wawrzynek (NOCS, 2009)

A design methodology for domain-optimized power-efficient supercomputing. - Marghoob Mohiyuddin; Mark Murphy; Leonid Oliker; John Shalf; John Wawrzynek; Samuel Williams 001 (SC, 2009)

A view of the parallel computing landscape. - Krste Asanovic; Rastislav Bodík; James Demmel; Tony M. Keaveny; Kurt Keutzer; John Kubiatowicz; Nelson Morgan; David A. Patterson 001; Koushik Sen; John Wawrzynek; David Wessel; Katherine A. Yelick (Commun. ACM, 2009)

High-throughput bayesian computing machine with reconfigurable hardware. - Mingjie Lin; Ilia A. Lebedev; John Wawrzynek (FPGA, 2010)

OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices. - Mingjie Lin; Ilia A. Lebedev; John Wawrzynek (FPL, 2010)

ParaLearn: a massively parallel, scalable system for learning interaction networks on FPGAs. - Narges Bani Asadi; Christopher W. Fletcher; Greg Gibeling; John Wawrzynek; Wing H. Wong; Garry P. Nolan (ICS, 2010)

MARC: A Many-Core Approach to Reconfigurable Computing. - Ilia A. Lebedev; Shaoyi Cheng; Austin Doupnik; James C. Martin; Christopher W. Fletcher; Daniel Burke; Mingjie Lin; John Wawrzynek (ReConFig, 2010)

Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations. - Mingjie Lin; Shaoyi Cheng; John Wawrzynek (ReConFig, 2010)

Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling. - Mingjie Lin; John Wawrzynek (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Exploring FPGA Routing Architecture Stochastically. - Mingjie Lin; John Wawrzynek; Abbas El Gamal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Advances and challenges of computing with FPGAs. - John Wawrzynek (CICC, 2011)

Bridging the GPGPU-FPGA efficiency gap. - Christopher W. Fletcher; Ilia A. Lebedev; Narges Bani Asadi; Daniel Burke; John Wawrzynek (FPGA, 2011)

Using many-core architectural templates for FPGA-based computing (abstract only). - Mingjie Lin; Shaoyi Cheng; John Wawrzynek (FPGA, 2011)

Should the academic community launch an open-source FPGA device and tools effort?: evening panel. - John Wawrzynek (FPGA, 2011)

Discriminatively Fortified Computing with Reconfigurable Digital Fabric. - Mingjie Lin; Yu Bai 004; John Wawrzynek (HASE, 2011)

RTP Payload Format for MIDI. - John Lazzaro; John Wawrzynek (RFC, 2011)

Chisel: constructing hardware in a Scala embedded language. - Jonathan Bachrach; Huy Vo; Brian C. Richards; Yunsup Lee; Andrew Waterman; Rimas Avizienis; John Wawrzynek; Krste Asanovic (DAC, 2012)

Exploiting Memory-Level Parallelism in Reconfigurable Accelerators. - Shaoyi Cheng; Mingjie Lin; Hao Jun Liu; Simon Scott; John Wawrzynek (FCCM, 2012)

Exploring Many-Core Design Templates for FPGAs and ASICs. - Ilia A. Lebedev; Christopher W. Fletcher; Shaoyi Cheng; James C. Martin; Austin Doupnik; Daniel Burke; Mingjie Lin; John Wawrzynek (Int. J. Reconfigurable Comput., 2012)

Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience. - Mingjie Lin; Yu Bai 004; John Wawrzynek (J. Electr. Comput. Eng., 2012)

Reconfigurable computing in the era of post-silicon scaling [panel discussion]. - Eric S. Chung; Doug Burger; Mike Butts; Jan Gray; Chuck Thacker; Kees A. Vissers; John Wawrzynek (FCCM, 2013)

Extracting memory-level parallelism through reconfigurable hardware traces. - Mingjie Lin; Shaoyi Cheng; John Wawrzynek (ReConFig, 2013)

Architectural synthesis of computational pipelines with decoupled memory access. - Shaoyi Cheng; John Wawrzynek (FPT, 2014)

The Swarm at the Edge of the Cloud. - Edward A. Lee; Björn Hartmann; John Kubiatowicz; Tajana Simunic Rosing; John Wawrzynek; David Wessel; Jan M. Rabaey; Kris Pister; Alberto L. Sangiovanni-Vincentelli; Sanjit A. Seshia; David T. Blaauw; Prabal Dutta; et al. (IEEE Des. Test, 2014)

The Cloud is Not Enough: Saving IoT from the Cloud. - Ben Zhang 003; Nitesh Mor; John Kolb; Douglas S. Chan; Ken Lutz; Eric Allman; John Wawrzynek; Edward A. Lee; John Kubiatowicz (HotStorage, 2015)

ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism. - Mingjie Lin; Shaoyi Cheng; Ronald F. DeMara; John Wawrzynek (Microprocess. Microsystems, 2015)

OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. - Hayden Kwok-Hay So; John Wawrzynek (FPGA, 2016)

Synthesis of statically analyzable accelerator networks from sequential programs. - Shaoyi Cheng; John Wawrzynek (ICCAD, 2016)

Toward standardized localization service. - Filip Lemic; Vlado Handziski; Nitesh Mor; Jan M. Rabaey; John Wawrzynek; Adam Wolisz (IPIN, 2016)

Localization as a feature of mmWave communication. - Filip Lemic; James C. Martin; Christopher Yarp; Douglas S. Chan; Vlado Handziski; Robert W. Brodersen; Gerhard P. Fettweis; Adam Wolisz; John Wawrzynek (IWCMC, 2016)

High Level Synthesis with a Dataflow Architectural Template. - Shaoyi Cheng; John Wawrzynek (CoRR, 2016)

Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). - Hayden Kwok-Hay So; John Wawrzynek (CoRR, 2016)

Toward a Global Data Infrastructure. - Nitesh Mor; Ben Zhang 003; John Kolb; Douglas S. Chan; Nikhil Goyal; Nicholas Sun; Ken Lutz; Eric Allman; John Wawrzynek; Edward A. Lee; John Kubiatowicz (IEEE Internet Comput., 2016)

Compressive sensing and sparse antenna arrays for indoor 3-D microwave imaging. - Simon Scott; John Wawrzynek (EUSIPCO, 2017)

OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. - Hayden Kwok-Hay So; John Wawrzynek (FPGA, 2017)

Synthesis of program binaries into FPGA accelerators with runtime dependence validation. - Shaoyi Cheng; Qijing Huang 001; John Wawrzynek (FPT, 2017)

Selection and Aggregation of Location Information Provisioning Services. - Filip Lemic; Vlado Handziski; Mladen Miksa; Jan M. Rabaey; John Wawrzynek; Adam Wolisz (ICCCN, 2017)

SLSR: A flexible middleware localization service architecture. - Filip Lemic; Vlado Handziski; Ivan Azcarate; John Wawrzynek; Jan M. Rabaey; Adam Wolisz (IPIN, 2017)

Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). - Hayden Kwok-Hay So; John Wawrzynek (CoRR, 2017)

NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads. - Guohao Dai; Tianhao Huang; Yu Wang 002; Huazhong Yang; John Wawrzynek (FCCM, 2018)

Receiver Adaptive Beamforming and Interference of Indoor Environments in mmWave. - James C. Martin; Robert W. Brodersen; John Wawrzynek (PIMRC, 2018)

AWStream: adaptive wide-area streaming analytics. - Ben Zhang 003; Xin Jin 008; Sylvia Ratnasamy; John Wawrzynek; Edward A. Lee (SIGCOMM, 2018)

GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. - Guohao Dai; Tianhao Huang; Yu Wang 002; Huazhong Yang; John Wawrzynek (ASP-DAC, 2019)

AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. - Qijing Huang 001; Ameer Haj-Ali; William S. Moses; John Xiang; Ion Stoica; Krste Asanovic; John Wawrzynek (FCCM, 2019)

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. - Yifan Yang; Qijing Huang 001; Bichen Wu; Tianjun Zhang; Liang Ma 003; Giulio Gambardella; Michaela Blott; Luciano Lavagno; Kees A. Vissers; John Wawrzynek; Kurt Keutzer (FPGA, 2019)

Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. - Qijing Huang 001; Christopher Yarp; Sagar Karandikar; Nathan Pemberton; Benjamin Brock; Liang Ma 003; Guohao Dai; Robert Quitt; Krste Asanovic; John Wawrzynek (ICCAD, 2019)

Algorithm-hardware Co-design for Deformable Convolution. - Qijing Huang 001; Dequan Wang; Yizhao Gao 002; Yaohui Cai; Zhen Dong 003; Bichen Wu; Kurt Keutzer; John Wawrzynek (EMC2@NeurIPS, 2019)

Antenna Array Geometries for Directional Wireless Networks. - James C. Martin; Robert W. Brodersen; John Wawrzynek (WCNC, 2019)

AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. - Ameer Haj Ali; Qijing Huang 001; William S. Moses; John Xiang; Ion Stoica; Krste Asanovic; John Wawrzynek (CoRR, 2019)

HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing. - Guohao Dai; Tianhao Huang; Yu Wang 002; Huazhong Yang; John Wawrzynek (IEEE Trans. Computers, 2019)

AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. - Ameer Haj-Ali; Qijing (Jenny) Huang; William S. Moses; John Xiang; Krste Asanovic; John Wawrzynek; Ion Stoica (MLSys, 2020)

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. - Yukio Miyasaka; Masahiro Fujita; Alan Mishchenko; John Wawrzynek (VLSI-SoC (Selected Papers), 2020)

ProTuner: Tuning Programs with Monte Carlo Tree Search. - Ameer Haj-Ali; Hasan Genc; Qijing Huang 001; William S. Moses; John Wawrzynek; Krste Asanovic; Ion Stoica (CoRR, 2020)

CoDeNet: Algorithm-hardware Co-design for Deformable Convolution. - Zhen Dong 003; Dequan Wang; Qijing Huang 001; Yizhao Gao 002; Yaohui Cai; Bichen Wu; Kurt Keutzer; John Wawrzynek (CoRR, 2020)

HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. - Zhen Dong 003; Yizhao Gao 002; Qijing Huang 001; John Wawrzynek; Hayden K. H. So; Kurt Keutzer (FCCM, 2021)

CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. - Qijing Huang 001; Dequan Wang; Zhen Dong 003; Yizhao Gao 002; Yaohui Cai; Tian Li; Bichen Wu; Kurt Keutzer; John Wawrzynek (FPGA, 2021)

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. - Qijing Huang 001; Aravind Kalaiah; Minwoo Kang; James Demmel; Grace Dinh; John Wawrzynek; Thomas Norell; Yakun Sophia Shao (ISCA, 2021)

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. - Qijing Huang 001; Charles Hong; John Wawrzynek; Mahesh Subedar; Yakun Sophia Shao (ISPASS, 2022)

Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. - Benjamin Lukas Cajus Barzen; Arya Reais-Parsi; Eddie Hung; Minwoo Kang; Alan Mishchenko; Jonathan W. Greene; John Wawrzynek (DATE, 2023)

SPADES: A Productive Design Flow for Versal Programmable Logic. - Tan Nguyen; Zachary Blair; Stephen Neuendorffer; John Wawrzynek (FPL, 2023)

Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas. - Arash Ardakani; Minwoo Kang; Kevin He; Vighnesh M. Iyer; Suhong Moon; John Wawrzynek (DAC, 2024)

Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. - Yukio Miyasaka; Alan Mishchenko; John Wawrzynek; Nicholas J. Fraser (FCCM, 2024)

Chip Placement with Diffusion. - Vint Lee; Chun Deng; Leena Elzeiny; Pieter Abbeel; John Wawrzynek (CoRR, 2024)

DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. - Arash Ardakani; Minwoo Kang; Kevin He; Qijing Huang 001; Vighnesh M. Iyer; Suhong Moon; John Wawrzynek (ASP-DAC, 2025)

High-Effort Logic Synthesis Using Randomized Transduction. - Yukio Miyasaka; Alan Mishchenko; John Wawrzynek; Dino Ruic; Xiaoqing Xu (ASP-DAC, 2025)

High-Throughput SAT Sampling. - Arash Ardakani; Minwoo Kang; Kevin He; Qijing Huang 001; John Wawrzynek (DATE, 2025)

Lessons from 40 Years of Reconfigurable Computing. - John Wawrzynek (FPGA, 2025)

Recurrent CircuitSAT Sampling for Sequential Circuits. - Arash Ardakani; Kevin He; John Wawrzynek (CoRR, 2025)