A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. - Gicheol Shin; Donguk Seo; Jaerok Kim; Johnny Rhe; Eunyoung Lee; Seonho Kim; Soyoun Jeong; Jong Hwan Ko; Yoonmyung Lee (ESSDERC, 2021)

A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators. - Eunyoung Lee; Taeyoung Han; Donguk Seo; Gicheol Shin; Jaerok Kim; Seonho Kim; Soyoun Jeong; Johnny Rhe; Jaehyun Park 012; Jong Hwan Ko; Yoonmyung Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

VW-SDK: Efficient Convolutional Weight Mapping Using Variable Windows for Processing-In-Memory Architectures. - Johnny Rhe; Sungmin Moon; Jong Hwan Ko (DATE, 2022)

VWC-SDK: Convolutional Weight Mapping Using Shifted and Duplicated Kernel With Variable Windows and Channels. - Johnny Rhe; Sungmin Moon; Jong Hwan Ko (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Kernel Shape Control for Row-Efficient Convolution on Processing-In-Memory Arrays. - Johnny Rhe; Kang Eun Jeon; Joo Chan Lee; Seongmoon Jeong; Jong Hwan Ko (ICCAD, 2023)

DCR: Decomposition-Aware Column Re-Mapping for Stuck-At-Fault Tolerance in ReRAM Arrays. - Hyeonsu Bang; Kang Eun Jeon; Johnny Rhe; Jong Hwan Ko (ICCD, 2023)

Weight-Aware Activation Mapping for Energy-Efficient Convolution on PIM Arrays. - Kang Eun Jeon; Johnny Rhe; Hyeonsu Bang; Jong Hwan Ko (ISLPED, 2023)

PAIRS: Pruning-AIded Row-Skipping for SDK-Based Convolutional Weight Mapping in Processing-In-Memory Architectures. - Johnny Rhe; Kang Eun Jeon; Jong Hwan Ko (ISLPED, 2023)

An Efficient Ventricular Arrhythmias Detection on Microcontrollers with Optimized 1D CNN. - Chanwook Hwang; Jaehyeon So; Johnny Rhe; Jiyoon Kim; Juhong Park; Kang Eun Jeon; Jong Hwan Ko (AICAS, 2024)

ConvMapSim: Modeling and Simulating Convolutional Weight Mapping for PIM Arrays. - Kang Eun Jeon; Wooram Seo; Johnny Rhe; Jong Hwan Ko (AICAS, 2024)

KARS: Kernel-Grouping Aided Row-Skipping for SDK-based Weight Compression in PIM Arrays. - Juhong Park; Johnny Rhe; Jong Hwan Ko (ISCAS, 2024)

Row-Efficient Pruning for In-Memory Convolutional Weight Mapping. - Johnny Rhe; Jong Hwan Ko (ISOCC, 2024)

KERNTROL: Kernel Shape Control Toward Ultimate Memory Utilization for In-Memory Convolutional Weight Mapping. - Johnny Rhe; Kang Eun Jeon; Joo Chan Lee; Seongmoon Jeong; Jong Hwan Ko (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Low-Rank Compression for IMC Arrays. - Kang Eun Jeon; Johnny Rhe; Jong Hwan Ko (DATE, 2025)

Input/mapping precision controllable digital CIM with adaptive adder tree architecture for flexible DNN inference. - Juhong Park; Johnny Rhe; Chanwook Hwang; Jaehyeon So; Jong Hwan Ko (J. Syst. Archit., 2025)

GAROS: Genetic algorithm-aided row-skipping for shift and duplicate kernel mapping in processing-in-memory architectures. - Johnny Rhe; Kang Eun Jeon; Jong Hwan Ko (J. Syst. Archit., 2025)

Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays. - Kang Eun Jeon; Sangheum Yeon; Jinhee Kim; Hyeonsu Bang; Johnny Rhe; Jong Hwan Ko (CoRR, 2025)