Some Characteristics of Universal Cell Nets. - Jon T. Butler; Kenneth J. Breeding (IEEE Trans. Computers, 1973)

A Note on Cellular Automata Simulations - Jon T. Butler (Inf. Control., 1974)

On the Number of Functions Realized by Cascades and Disjunctive Networks. - Jon T. Butler (IEEE Trans. Computers, 1975)

Restricted Cellular Networks. - Jon T. Butler (IEEE Trans. Computers, 1976)

Analysis and Design of Fanout-Free Networks of Positive Symmetric Gates. - Jon T. Butler (J. ACM, 1978)

Asymptotic Aproximations for the Number of Fanout-Free Functions. - Edward A. Bender; Jon T. Butler (IEEE Trans. Computers, 1978)

Tandem Networks of Universal Cells. - Jon T. Butler (IEEE Trans. Computers, 1978)

Decomposable Maps in General Tessellation Structures. - Jon T. Butler (J. Comput. Syst. Sci., 1979)

Synthesis of One-Dimensional Binary Cellular Automata Systems from Composite Local Maps - Jon T. Butler (Inf. Control., 1979)

Synthesis of One-Dimensional Binary Scope-2 Flexible Cellular Systems from Initial Final Configuration Pairs - Patrick E. White; Jon T. Butler (Inf. Control., 1980)

Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms. - Jon T. Butler (IEEE Trans. Computers, 1981)

On the relationship between propagating context-dependent lindenmayer systems and cellular automata systems. - Jon T. Butler (Inf. Sci., 1982)

Enumeration of Structured Flowcharts - Edward A. Bender; Jon T. Butler (J. ACM, 1985)

Multiple-Valued Logic - Guest Editor's Introduction. - Jon T. Butler (Computer, 1988)

Multiple-Valued CCD Circuits. - Jon T. Butler; Hans G. Kerkhoff (Computer, 1988)

On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions. - Edward A. Bender; Jon T. Butler (IEEE Trans. Computers, 1989)

A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. - Jon T. Butler; Hans G. Kerkhoff; Siep Onneweer (ISMVL, 1990)

HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. - John M. Yurchak; Jon T. Butler (ISMVL, 1990)

On the Equivalence of Cost Functions in the Design of Circuits by Costtable. - Jon T. Butler; Kriss A. Schueller (IEEE Trans. Computers, 1990)

A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs. - Joo-Kang Lee; Jon T. Butler (IEEE Trans. Computers, 1990)

Worst Case Number of Terms in Symmetric Multiple-Valued Functions. - Jon T. Butler; Kriss A. Schueller (ISMVL, 1991)

The Design of Current Mode CMOS Multiple-Valued Circuits. - Young-hoon Chang; Jon T. Butler (ISMVL, 1991)

Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. - Parthasarathy P. Tirumalai; Jon T. Butler (IEEE Trans. Computers, 1991)

Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991. - Susan W. Butler; Jon T. Butler (ISMVL, 1992)

Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing. - Gerhard W. Dueck; Robert C. Earle; Parthasarathy P. Tirumalai; Jon T. Butler (ISMVL, 1992)

On the Design of Cost-Tables for Realizing Multiple-Valued Circuits. - Kriss A. Schueller; Jon T. Butler (IEEE Trans. Computers, 1992)

Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing. - Cem Yildirim; Jon T. Butler; Chyan Yang (ISMVL, 1993)

Multiple-Valued Combinational Circuits with Feedback. - Jon T. Butler; Tsutomu Sasao (ISMVL, 1994)

Multiple-Valued Logic Operations with Universal Literals. - Gerhard W. Dueck; Jon T. Butler (ISMVL, 1994)

A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1994)

Planar Multiple-Valued Decision Diagrams. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1995)

Planarity in ROMDD's of Multiple-Valued Symmetric Functions. - Jon T. Butler; J. L. Nowlin; Tsutomu Sasao (ISMVL, 1996)

A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1996)

Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions. - Tsutomu Sasao; Jon T. Butler (ISMVL, 1997)

Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions. - Jon T. Butler; David S. Herscovici; Tsutomu Sasao; Robert J. Barton III (IEEE Trans. Computers, 1997)

Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. - Kriss A. Schueller; Jon T. Butler (IEEE Trans. Computers, 1997)

On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels. - Jon T. Butler; Tsutomu Sasao (ISMVL, 1998)

Experiments on FPRM Expressions for Partially Symmetric Logic Functions. - Svetlana N. Yanushkevich; Jon T. Butler; Gerhard W. Dueck; Vlad P. Shmerko (ISMVL, 2000)

Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions". - Jon T. Butler; Gerhard W. Dueck; Vlad P. Shmerko; Svetlana N. Yanushkevich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

On the minimization of SOPs for bi-decomposition functions. - Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2001)

On the number of generators for transeunt triangles. - Jon T. Butler; Gerhard W. Dueck; Svetlana N. Yanushkevich; Vlad P. Shmerko (Discret. Appl. Math., 2001)

Worst and Best Irredundant Sum-of-Products Expressions. - Tsutomu Sasao; Jon T. Butler (IEEE Trans. Computers, 2001)

Bi-Partition of Shared Binary Decision Diagrams. - Munehiro Matsuura; Tsutomu Sasao; Jon T. Butler; Yukihiro Iguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

On the Average Path Length in Decision Diagrams of Multiple-Valued Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2003)

A fast method to derive minimum SOPs for decomposable functions. - Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2004)

Programmable Numerical Function Generators: Architectures and Synthesis Method. - Tsutomu Sasao; Shinobu Nagayama; Jon T. Butler (FPL, 2005)

Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. - Shinobu Nagayama; Alan Mishchenko; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2005)

Average Path Length of Binary Decision Diagrams. - Jon T. Butler; Tsutomu Sasao; Munehiro Matsuura (IEEE Trans. Computers, 2005)

Implementation of LPM Address Generators on FPGAs. - Hui Qin; Tsutomu Sasao; Jon T. Butler (ARC, 2006)

Programmable numerical function generators based on quadratic approximation: architecture and synthesis method. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2006)

Implementation of Multiple-Valued CAM Functions by LUT Cascades. - Tsutomu Sasao; Jon T. Butler (ISMVL, 2006)

Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Numerical Function Generators Using Edge-Valued Binary Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ASP-DAC, 2007)

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (DSD, 2007)

Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Numerical Function Generators Using LUT Cascades. - Tsutomu Sasao; Shinobu Nagayama; Jon T. Butler (IEEE Trans. Computers, 2007)

Programmable Numerical Function Generators for Two-Variable Functions. - Shinobu Nagayama; Jon T. Butler; Tsutomu Sasao (DSD, 2008)

Numerical function generators using bilinear interpolation. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (FPL, 2008)

Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2009)

A Quaternary Decision Diagram Machine and the Optimization of its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (ISMVL, 2009)

Progress in Applications of Boolean Functions - Tsutomu Sasao; Jon T. Butler (Morgan & Claypool Publishers, 2009)

Enumeration of Bent Boolean Functions by Reconfigurable Computer. - J. L. Shafer; S. W. Schneider; Jon T. Butler; Pantelimon Stanica (FCCM, 2010)

Floating-Point Numeric Function Generators Based on Piecewise-Split EVMDDs. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2010)

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Inf. Syst., 2010)

A Quaternary Decision Diagram Machine: Optimization of Its Code. - Tsutomu Sasao; Hiroki Nakahara; Munehiro Matsuura; Yoshifumi Kawamura; Jon T. Butler (IEICE Trans. Inf. Syst., 2010)

Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

On the number of segments needed in a piecewise linear approximation. - C. L. Frenzen; Tsutomu Sasao; Jon T. Butler (J. Comput. Appl. Math., 2010)

Index to Constant Weight Codeword Converter. - Jon T. Butler; Tsutomu Sasao (ARC, 2011)

Fast Hardware Computation of x Mod z. - Jon T. Butler; Tsutomu Sasao (IPDPS Workshops, 2011)

Numeric Function Generators Using Piecewise Arithmetic Expressions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2011)

A fast segmentation algorithm for piecewise polynomial numeric function generators. - Jon T. Butler; C. L. Frenzen; Njuguna Macaria; Tsutomu Sasao (J. Comput. Appl. Math., 2011)

Hardware Index to Permutation Converter. - Jon T. Butler; Tsutomu Sasao (IPDPS Workshops, 2012)

Analysis of Multi-state Systems with Multi-state Components Using EVMDDs. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2012)

Hardware Index to Set Partition Converter. - Jon T. Butler; Tsutomu Sasao (ARC, 2013)

Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2013)

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Mitchell A. Thornton; Theodore W. Manikas (ISMVL, 2014)

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Mitchell A. Thornton; Theodore W. Manikas (IEICE Trans. Inf. Syst., 2014)

EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2014)

Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2014)

Applications of Zero-Suppressed Decision Diagrams - Tsutomu Sasao; Jon T. Butler (Morgan & Claypool Publishers, 2014)

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Mitchell A. Thornton; Theodore W. Manikas (ISMVL, 2015)

High-Speed Hardware Partition Generation. - Jon T. Butler; Tsutomu Sasao (ACM Trans. Reconfigurable Technol. Syst., 2015)

An Efficient Heuristic for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2016)

A set partition number system. - Jon T. Butler; Tsutomu Sasao (Australas. J Comb., 2016)

Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications. - Vincent C. Gaudet; Jon T. Butler; Robert Wille; Naofumi Homma (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

A Parallel Approach in Computing Correlation Immunity up to Six Variables. - Carole J. Etherington; Matthew W. Anderson; Eric Bach 001; Jon T. Butler; Pantelimon Stanica (Int. J. Found. Comput. Sci., 2016)

An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2017)

A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Inf. Syst., 2017)

Decomposition of Index Generation Functions Using a Monte Carlo Method. - Tsutomu Sasao; Jon T. Butler (Advanced Logic Synthesis, 2018)

An Exact Method to Enumerate Decomposition Charts for Index Generation Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2018)

An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2018)

An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (FLAP, 2018)

Realizing all Index Generation Functions by the Row-Shift Method. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2019)

Maximally Asymmetric Multiple-Valued Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2019)

A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2019)

Properties of Multiple-Valued Partition Functions. - Jon T. Butler; Tsutomu Sasao; Shinobu Nagayama (ISMVL, 2020)

On Optimum Linear Decomposition of Symmetric Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2020)

Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2021)

Linear Decompositions for Multi-Valued Input Classification Functions. - Tsutomu Sasao; Jon T. Butler (ISMVL, 2021)

On the Sensitivity of Boolean and Multiple-Valued Symmetric Functions. - Jon T. Butler; Tsutomu Sasao (ISMVL, 2022)

On Decision Diagrams for Maximally Asymmetric Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2022)

A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (J. Multiple Valued Log. Soft Comput., 2022)

Decomposition-Based Representation of Symmetric Multiple-Valued Functions. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (ISMVL, 2023)

On the distribution of sensitivities of symmetric Boolean functions. - Jon T. Butler; Tsutomu Sasao; Shinobu Nagayama (CoRR, 2023)

On Representation of Maximally Asymmetric Functions Based on Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (FLAP, 2023)

Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler (IEICE Trans. Inf. Syst., 2024)

Representation of Rotation Symmetric Multiple-Valued Functions Using Decision Diagrams. - Shinobu Nagayama; Tsutomu Sasao; Jon T. Butler; Martin Lukac (ISMVL, 2025)