Parameterized Logic Power Consumption Models for FPGA based Systems. - Jonathan A. Clarke; Altaf Abdul Gaffar; George A. Constantinides (FPL, 2005)

High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. - Jonathan A. Clarke; George A. Constantinides (FPL, 2006)

PowerBit - power aware arithmetic bit-width optimization. - Altaf Abdul Gaffar; Jonathan A. Clarke; George A. Constantinides (FPT, 2006)

Modeling of glitch effects in FPGA based arithmetic circuits. - Altaf Abdul Gaffar; Jonathan A. Clarke; George A. Constantinides (FPT, 2006)

Fast word-level power models for synthesis of FPGA-based arithmetic. - Jonathan A. Clarke; Altaf Abdul Gaffar; George A. Constantinides; Peter Y. K. Cheung (ISCAS, 2006)

On the feasibility of early routing capacitance estimation for FPGAs. - Jonathan A. Clarke; George A. Constantinides; Peter Y. K. Cheung (FPL, 2007)

Glitch-aware output switching activity from word-level statistics. - Jonathan A. Clarke; George A. Constantinides; Peter Y. K. Cheung; Alastair M. Smith (ISCAS, 2008)

Word-length selection for power minimization via nonlinear optimization. - Jonathan A. Clarke; George A. Constantinides; Peter Y. K. Cheung (ACM Trans. Design Autom. Electr. Syst., 2009)