Mismatch analysis and statistical design at 65 nm and below. - Larry T. Pileggi; Gökçe Keskin; Xin Li 001; Ken Mai; Jonathan E. Proesel (CICC, 2008)

A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. - Jonathan E. Proesel; Lawrence T. Pileggi (CICC, 2008)

Statistical modeling and post manufacturing configuration for scaled analog CMOS. - Gokce Keskin; Jonathan E. Proesel; Larry T. Pileggi (CICC, 2010)

An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. - Jonathan E. Proesel; Gokce Keskin; Jean-Olivier Plouchart; Lawrence T. Pileggi (CICC, 2010)

Post-silicon calibration of analog CMOS using phase-change memory cells. - Cheng-Yuan Wen; Jeyanandh Paramesh; Larry T. Pileggi; Jing Li 073; SangBum Kim; Jonathan E. Proesel; Chung Lam (ESSCIRC, 2011)

Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. - Gokce Keskin; Jonathan E. Proesel; Jean-Olivier Plouchart; Lawrence T. Pileggi (IEEE J. Solid State Circuits, 2011)

25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS. - Jonathan E. Proesel; Clint Schow; Alexander V. Rylyakov (ISSCC, 2012)

Ultra-Low-Power 10 to 285 Gb/s CMOS-Driven VCSEL-Based Optical Links [Invited]. - Jonathan E. Proesel; Benjamin G. Lee; Alexander V. Rylyakov; Christian W. Baks; Clint L. Schow (JOCN, 2012)

Optical receivers using DFE-IIR equalization. - Jonathan E. Proesel; Alexander V. Rylyakov; Clint Schow (ISSCC, 2013)

A 56.1Gb/s NRZ modulated 850nm VCSEL-based optical link. - Daniel M. Kuchta; Clint L. Schow; Alexander V. Rylyakov; Jonathan E. Proesel; Fuad E. Doany; Christian W. Baks; B. H. Hamel-Bissell; Chris Kocot; L. Graham; R. Johnson; Gary Landry; E. Shaw; et al. (OFC/NFOEC, 2013)

35-Gb/s VCSEL-Based optical link using 32-nm SOI CMOS circuits. - Jonathan E. Proesel; Benjamin G. Lee; Christian W. Baks; Clint L. Schow (OFC/NFOEC, 2013)

Exploring the limits of high-speed receivers for multimode VCSEL-based optical links. - Nicolas Dupuis; Daniel M. Kuchta; Fuad E. Doany; Alexander V. Rylyakov; Jonathan E. Proesel; Christian W. Baks; Clint L. Schow; S. Luong; C. Xie; L. Wang; S. Huang; K. Jackson; et al. (OFC, 2014)

30Gbps optical link utilizing heterogeneously integrated III-V/Si photonics and CMOS circuits. - Nicolas Dupuis; Benjamin G. Lee; Jonathan E. Proesel; Alexander V. Rylyakov; Renato Rimolo-Donadio; Christian W. Baks; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Robert S. Guzzon; Brian R. Koch; Daniel K. Sparacin; et al. (OFC, 2014)

64Gb/s transmission over 57m MMF using an NRZ modulated 850nm VCSEL. - Daniel M. Kuchta; Alexander V. Rylyakov; Clint L. Schow; Jonathan E. Proesel; Christian W. Baks; Petter Westbergh; Johan S. Gustavsson; Anders Larsson (OFC, 2014)

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (ISSCC, 2015)

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. - Benjamin G. Lee; Renato Rimolo-Donadio; Alexander V. Rylyakov; Jonathan E. Proesel; John F. Bulzacchelli; Christian W. Baks; Mounir Meghelli; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Jae-Hyuk Shin; Brian R. Koch; et al. (OFC, 2015)

A WDM 4×28Gbps integrated silicon photonic transmitter driven by 32nm CMOS driver ICs. - Anand Ramaswamy; Jonathan E. Roth; Erik J. Norberg; Robert S. Guzzon; Jae-Hyuk Shin; J. T. Imamura; Brian R. Koch; Daniel K. Sparacin; Gregory A. Fish; Benjamin G. Lee; Renato Rimolo-Donadio; Christian W. Baks; et al. (OFC, 2015)

A 25 Gb/s burst-mode receiver for low latency photonic switch networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Clint Schow; Mounir Meghelli (OFC, 2015)

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (IEEE J. Solid State Circuits, 2015)

Monolithic silicon photonics at 25 Gb/s. - Jason S. Orcutt; Douglas M. Gill; Jonathan E. Proesel; John J. Ellis-Monaghan; Folkert Horst; Tymon Barwicz; Chi Xiong; Frederick G. Anderson; Ankur Agrawal; Yves Martin; Christian W. Baks; Marwan Khater; et al. (OFC, 2016)

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. - Alessandro Cevrero; Ilter Özkaya; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; Benjamin G. Lee; et al. (ISSCC, 2017)

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2017)

FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. - Benjamin G. Lee; Nicolas Dupuis; Jason Orcutt; Javier Ayala; Karen Nummy; Herschel A. Ainspan; Jonathan E. Proesel; Christian W. Baks; Douglas M. Gill; Mounir Meghelli; William M. J. Green (OFC, 2018)

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. - Ilter Özkaya; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Thomas Morf; Matthias Braendli; Daniel M. Kuchta; Lukas Kull; Christian W. Baks; Jonathan E. Proesel; Marcel A. Kossel; Danny Luu; et al. (IEEE J. Solid State Circuits, 2018)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (ISSCC, 2019)

Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). - Daniel M. Kuchta; Jonathan E. Proesel; Fuad E. Doany; Wooram Lee; Timothy O. Dickson; Herschel A. Ainspan; Mounir Meghelli; Petar K. Pepeljugoski; Xiaoxiong Gu; Michael P. Beakes; Mark Schultz; Marc Taubenblatt; et al. (OFC, 2019)

Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. - Benjamin G. Lee; Nicolas Dupuis; Fuad E. Doany; Laurent Schares; Nicolas Boyer; Nathalie Normand; Herschel A. Ainspan; Christian W. Baks; Jonathan E. Proesel; Isabel De Sousa; Mounir Meghelli; Marc A. Taubenblatt (OFC, 2019)

An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability. - Nicolas Dupuis; Jonathan E. Proesel; Nicolas Boyer; Herschel A. Ainspan; Christian W. Baks; Fuad E. Doany; Elaine Cyr; Benjamin G. Lee (OFC, 2020)

A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS. - Jonathan E. Proesel; Nicolas Dupuis; Herschel A. Ainspan; Christian W. Baks; Fuad E. Doany; Nicolas Boyer; Elaine Cyr; Benjamin G. Lee (VLSI Circuits, 2020)

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; John F. Bulzacchelli; Marcel A. Kossel; Pier Andrea Francese; Thomas Morf; Jonathan E. Proesel; Herschel A. Ainspan; Matthias Brändli; Mounir Meghelli (CICC, 2024)

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1 mathrm{V}_{ text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. - Zeynep Toprak Deniz; Timothy O. Dickson; Martin Cochet; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Matthias Brändli; Thomas Morf; Michael P. Beakes; Mounir Meghelli (VLSI Technology and Circuits, 2024)