Parallel controller synthesis from a Petri net specification. - Krzysztof Bilinski; Erik L. Dagless; Jonathan M. Saul; Marian Adamski (EURO-DAC, 1994)

DART: delay and routability driven technology mapping for LUT based FPGAs. - Aiguo Lu; Erik L. Dagless; Jonathan M. Saul (ICCD, 1995)

Behavioral Synthesis of Complex Parallel Controllers. - Krzysztof Bilinski; Erik L. Dagless; Jonathan M. Saul (VLSI Design, 1996)