A low-power 2.5-GHz 90-nm level 1 cache and memory management unit. - Jonathan R. Haigh; Michael W. Wilkerson; Jay B. Miller; Timothy S. Beatty; Stephen J. Strazdus; Lawrence T. Clark (IEEE J. Solid State Circuits, 2005)

High performance set associative translation lookaside buffers for low power microprocessors. - Jonathan R. Haigh; Lawrence T. Clark (Integr., 2008)

Reducing process variation impact on replica-timed static random access memory sense timing. - Nishith N. Desai; Jonathan R. Haigh; Lawrence T. Clark (Integr., 2009)