FERMTOR: A Tunable Multiprocessor Architecture. - Jonathan Rose; Wayne M. Loucks; Zvonko G. Vranesic (IEEE Micro, 1985)

LocusRoute: A Parallel Global Router for Standard Cells. - Jonathan Rose (DAC, 1988)

Temperature measurement of simulated annealing placements. - Jonathan Rose; Wolfgang Klebsch; Jürgen Wolf (ICCAD, 1988)

The Parallel Decomposition and Implementation of an Integrated Circuit Global Router. - Jonathan Rose (PPOPP/PPEALS, 1988)

Parallel standard cell placement algorithms with quality equivalent to simulated annealing. - Jonathan Rose; W. Martin Snelgrove; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. - Robert J. Francis; Jonathan Rose; Kevin Chung (DAC, 1990)

Parallel global routing for standard cells. - Jonathan Rose (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Temperature measurement and equilibrium dynamics of simulated annealing placements. - Jonathan Rose; Wolfgang Klebsch; Jürgen Wolf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. - Jonathan Rose; Robert J. Francis; David M. Lewis; Paul Chow (IEEE J. Solid State Circuits, 1990)

Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. - Robert J. Francis; Jonathan Rose; Zvonko G. Vranesic (DAC, 1991)

Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). - Jonathan Rose (DAC, 1991)

Technology Mapping on Lookup Table-Based FPGAs for Performance. - Robert J. Francis; Jonathan Rose; Zvonko G. Vranesic (ICCAD, 1991)

Flexibility of interconnection structures for field-programmable gate arrays. - Jonathan Rose; Stephen Brown 003 (IEEE J. Solid State Circuits, 1991)

TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. - Kevin Chung; Jonathan Rose (DAC, 1992)

Improving FPGA Routing Architectures Using Architecture and CAD Interactions. - Benjamin Tseng; Jonathan Rose; Stephen Brown 003 (ICCD, 1992)

A detailed router for field-programmable gate arrays. - Stephen Brown 003; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

The effect of logic block architecture on FPGA performance. - Satwant Singh; Jonathan Rose; Paul Chow; David M. Lewis (IEEE J. Solid State Circuits, 1992)

Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). - Jonathan Rose (DAC, 1993)

Architecture of field-programmable gate arrays. - Jonathan Rose; Abbas El Gamal; Alberto L. Sangiovanni-Vincentelli (Proc. IEEE, 1993)

Synthesis method for field programmable gate arrays. - Alberto L. Sangiovanni-Vincentelli; Abbas El Gamal; Jonathan Rose (Proc. IEEE, 1993)

A stochastic model to predict the routability of field-programmable gate arrays. - Stephen Dean Brown; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Definition and solution of the memory packing problem for field-programmable systems. - David Karchmer; Jonathan Rose (ICCAD, 1994)

Using Architectural "Families" to Increase FPGA Speed and Density. - Vaughn Betz; Jonathan Rose (FPGA, 1995)

Architecture of Centralized Field-Configurable Memory. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (FPGA, 1995)

Characterization and Parameterized Random Generation of Digital Circuits. - Michael D. Hutton; Jerry P. Grossman; Jonathan Rose; Derek G. Corneil (DAC, 1996)

Directional bias and non-uniformity in FPGA global routing architectures. - Vaughn Betz; Jonathan Rose (ICCAD, 1996)

FPGA and CPLD Architectures: A Tutorial. - Stephen Brown 003; Jonathan Rose (IEEE Des. Test Comput., 1996)

Generation of Synthetic Sequential Benchmark Circuits. - Michael D. Hutton; Jonathan Rose; Derek G. Corneil (FPGA, 1997)

Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. - Jonathan Rose; Dwight D. Hill (FPGA, 1997)

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (FPGA, 1997)

VPR: A new packing, placement and routing tool for FPGA research. - Vaughn Betz; Jonathan Rose (FPL, 1997)

A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. - Mohammed A. S. Khalid; Jonathan Rose (FPGA, 1998)

Constraints from Hell: How to Tell Makes a Good FPGA (Panel). - Jonathan Rose; Sinan Kaptanoglu; Clive McCarthy; Rob Smith; Sandip Vij; Steve Taylor (FPGA, 1998)

A Fast Routability-Driven Router for FPGAs. - Jordan S. Swartz; Vaughn Betz; Jonathan Rose (FPGA, 1998)

How Much Logic Should Go in an FPGA Logic Block? - Vaughn Betz; Jonathan Rose (IEEE Des. Test Comput., 1998)

Characterization and parameterized generation of synthetic combinational benchmark circuits. - Michael D. Hutton; Jonathan Rose; Jerry P. Grossman; Derek G. Corneil (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Effect of the prefabricated routing track distribution on FPGA area-efficiency. - Vaughn Betz; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 1998)

The Transmogrifier-2: a 1 million gate rapid-prototyping system. - David M. Lewis; David R. Galloway; Marcus van Ierssel; Jonathan Rose; Paul Chow (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Architecture and CAD for Deep-Submicron FPGAS - Vaughn Betz; Jonathan Rose; Alexander Marquardt (Kluwer, 1999)

FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. - Vaughn Betz; Jonathan Rose (FPGA, 1999)

Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. - Alexander Marquardt; Vaughn Betz; Jonathan Rose (FPGA, 1999)

Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. - Yaska Sankar; Jonathan Rose (FPGA, 1999)

Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems. - Mohammed A. S. Khalid; Jonathan Rose (IPPS/SPDP Workshops, 1999)

Equivalence classes of clone circuits for physical-design benchmarking. - Michael D. Hutton; Jonathan Rose (ISCAS (6), 1999)

Applications of clone circuits to issues in physical-design. - Michael D. Hutton; Jonathan Rose (ISCAS (6), 1999)

The design of an SRAM-based field-programmable gate array. I. Architecture. - Paul Chow; Soon Ong Seo; Jonathan Rose; Kevin Chung; Gerard Páez-Monzón; Immanuel Rahardja (IEEE Trans. Very Large Scale Integr. Syst., 1999)

The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. - Paul Chow; Soon Ong Seo; Jonathan Rose; Kevin Chung; Gerard Páez-Monzón; Immanuel Rahardja (IEEE Trans. Very Large Scale Integr. Syst., 1999)

The memory/logic interface in FPGAs with large embedded memory arrays. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Automatic generation of FPGA routing architectures from high-level descriptions. - Vaughn Betz; Jonathan Rose (FPGA, 2000)

Timing-driven placement for FPGAs. - Alexander Marquardt; Vaughn Betz; Jonathan Rose (FPGA, 2000)

Real-time, frame-rate face detection on a configurable hardware system (poster abstract). - Rob McCready; Jonathan Rose (FPGA, 2000)

A novel and efficient routing architecture for multi-FPGA systems. - Mohammed A. S. Khalid; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Speed and area tradeoffs in cluster-based FPGA architectures. - Alexander Marquardt; Vaughn Betz; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Panel: (When) Will FPGAs Kill ASICs? - Rob A. Rutenbar; Max Baron; Thomas Daniel; Rajeev Jayaraman; Zvi Or-Bach; Jonathan Rose; Carl Sechen (DAC, 2001)

Mixing buffers and pass transistors in FPGA routing architectures. - Mike Sheng; Jonathan Rose (FPGA, 2001)

Structural analysis and generation of synthetic digital circuits with memory. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Nearest neighbour interconnect architecture in deep submicron FPGAs. - Ajay Roopchansingh; Jonathan Rose (CICC, 2002)

EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. - William Chow; Jonathan Rose (FPGA, 2002)

Synthesizing datapath circuits for FPGAs with emphasis on area minimization. - Andy Gean Ye; Jonathan Rose; David M. Lewis (FPT, 2002)

Automatic generation of synthetic sequential benchmark circuits. - Michael D. Hutton; Jonathan Rose; Derek G. Corneil (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. - Andy Gean Ye; Jonathan Rose; David M. Lewis (CICC, 2003)

Video-Rate Stereo Depth Measurement on Programmable Hardware. - Ahmad Darabiha; Jonathan Rose; W. James MacLean (CVPR (1), 2003)

The StratixTM routing and logic architecture. - David M. Lewis; Vaughn Betz; David Jefferson; Andy Lee; Christopher Lane; Paul Leventis; Sandy Marquardt; Cameron McClintock; Bruce Pedersen; Giles Powell; Srinivas Reddy; Chris Wysocki; et al. (FPGA, 2003)

Automatic transistor and physical design of FPGA tiles from an architectural specification. - Ketan Padalia; Ryan Fung; Mark Bourgeault; Aaron Egier; Jonathan Rose (FPGA, 2003)

A high-speed ray tracing engine built on a field-programmable system. - Joshua Fender; Jonathan Rose (FPT, 2003)

A parameterized automatic cache generator for FPGAs. - Peter Yiannacouras; Jonathan Rose (FPT, 2003)

A synthesis oriented omniscient manual editor. - Tomasz S. Czajkowski; Jonathan Rose (FPGA, 2004)

Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. - Ian Kuon; Aaron Egier; Jonathan Rose (FPGA, 2004)

Hardware Accelerated Novel Protein Identification. - Anish Alex; Jonathan Rose; Ruth Isserlin-Weinberger; Christopher W. V. Hogue (FPL, 2004)

Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. - Andy Gean Ye; Jonathan Rose (FPT, 2004)

Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. - Jonathan Rose (ISMVL, 2004)

Synthetic circuit generation using clustering and iteration. - Paul D. Kundarewich; Jonathan Rose (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

The effect of LUT and cluster size on deep-submicron FPGA performance and density. - Elias Ahmed; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2004)

The microarchitecture of FPGA-based soft processors. - Peter Yiannacouras; Jonathan Rose; J. Gregory Steffan (CASES, 2005)

Design, layout and verification of an FPGA using automated tools. - Ian Kuon; Aaron Egier; Jonathan Rose (FPGA, 2005)

The Stratix II logic and routing architecture. - David M. Lewis; Elias Ahmed; Gregg Baeckler; Vaughn Betz; Mark Bourgeault; David Cashman; David R. Galloway; Mike Hutton; Christopher Lane; Andy Lee; Paul Leventis; Sandy Marquardt; et al. (FPGA, 2005)

A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. - Peter Jamieson; Jonathan Rose (FPL, 2005)

Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. - Andy Gean Ye; Jonathan Rose (FPL, 2005)

The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth. - Joshua Fender; Jonathan Rose; David R. Galloway (FPT, 2005)

Application-specific customization of soft processor microarchitecture. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (FPGA, 2006)

Invited Keynote 1: Closing the gap between FPGAs and ASICs. - Jonathan Rose (FPT, 2006)

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. - Ahmad Darabiha; W. James MacLean; Jonathan Rose (Mach. Vis. Appl., 2006)

Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. - Andy Gean Ye; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. - Peter Jamieson; Jonathan Rose (FPT, 2007)

FPGA Architecture: Survey and Challenges. - Ian Kuon; Russell Tessier; Jonathan Rose (Found. Trends Electron. Des. Autom., 2007)

Measuring the Gap Between FPGAs and ASICs. - Ian Kuon; Jonathan Rose (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Exploration and Customization of FPGA-Based Soft Processors. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

VESPA: portable, scalable, and flexible FPGA-based vector processors. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (CASES, 2008)

Automated transistor sizing for FPGA architecture exploration. - Ian Kuon; Jonathan Rose (DAC, 2008)

Modeling routing demand for early-stage FPGA architecture development. - Wei Mark Fang; Jonathan Rose (FPGA, 2008)

Area and delay trade-offs in the circuit and architecture design of FPGAs. - Ian Kuon; Jonathan Rose (FPGA, 2008)

Fine-grain performance scaling of soft vector processors. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (CASES, 2009)

FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. - Jason Luu; Keith Redmond; William Lo; Paul Chow; Lothar Lilge; Jonathan Rose (FCCM, 2009)

VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. - Jason Luu; Ian Kuon; Peter Jamieson; Ted Campbell; Andy Gean Ye; Wei Mark Fang; Jonathan Rose (FPGA, 2009)

Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (FPGA, 2009)

The evolution of architecture exploration of programmable devices. - Jonathan Rose (FPL, 2009)

Data parallel FPGA workloads: Software versus hardware. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (FPL, 2009)

Faster coevolution detection of proteins using maximum similar cliques. - Alex Rodionov; Alexandr Bezginov; Jonathan Rose; Elisabeth R. M. Tillier (BCB, 2010)

Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. - Peter A. Jamieson; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. - Jason Luu; Jason Helge Anderson; Jonathan Rose (FPGA, 2011)

The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. - Jonathan Rose; Guy G. Lemieux (FPGA, 2011)

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. - Henry Wong; Vaughn Betz; Jonathan Rose (FPGA, 2011)

A new, fast algorithm for detecting protein coevolution using maximum compatible cliques. - Alex Rodionov; Alexandr Bezginov; Jonathan Rose; Elisabeth R. M. Tillier (Algorithms Mol. Biol., 2011)

VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. - Jason Luu; Ian Kuon; Peter Jamieson; Ted Campbell; Andy Gean Ye; Wei Mark Fang; Kenneth B. Kent; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2011)

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design. - Ian Kuon; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2011)

The VTR project: architecture and CAD for FPGAs from verilog to routing. - Jonathan Rose; Jason Luu; Chi Wai Yu; Opal Densmore; Jeffrey Goeders; Andrew Somerville; Kenneth B. Kent; Peter Jamieson; Jason Helge Anderson (FPGA, 2012)

On the difficulty of pin-to-wire routing in FPGAs. - Niyati Shah; Jonathan Rose (FPL, 2012)

An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection. - Braiden Brousseau; Jonathan Rose (FPT, 2012)

Portable and scalable FPGA-based acceleration of a direct linear system solver. - Wei Zhang 222; Vaughn Betz; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2012)

Portable, Flexible, and Scalable Soft Vector Processors. - Peter Yiannacouras; J. Gregory Steffan; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Efficient methods for out-of-order load/store execution for high-performance soft processors. - Henry Wong; Vaughn Betz; Jonathan Rose (FPT, 2013)

On Hard Adders and Carry Chains in FPGAs. - Jason Luu; Conor McCullough; Sen Wang; Safeen Huda; Bo Yan; Charles Chiasson; Kenneth B. Kent; Jason Helge Anderson; Jonathan Rose; Vaughn Betz (FCCM, 2014)

Towards interconnect-adaptive packing for FPGAs. - Jason Luu; Jonathan Rose; Jason Helge Anderson (FPGA, 2014)

VTR 7.0: Next Generation Architecture and CAD System for FPGAs. - Jason Luu; Jeffrey Goeders; Michael Wainberg; Andrew Somerville; Thien Yu; Konstantin Nasartschuk; Miad Nasr; Sen Wang; Tim Liu; Nooruddin Ahmed; Kenneth B. Kent; Jason Helge Anderson; et al. (ACM Trans. Reconfigurable Technol. Syst., 2014)

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. - Henry Wong; Vaughn Betz; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Performance characterization of mobile GP-GPUs. - Fitsum Assamnew Andargie; Jonathan Rose (AFRICON, 2015)

Automatic FPGA system and interconnect construction with multicast and customizable topology. - Alex Rodionov; Jonathan Rose (FPT, 2015)

High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. - Henry Wong; Vaughn Betz; Jonathan Rose (FCCM, 2016)

Fine-Grained Interconnect Synthesis. - Alex Rodionov; David Biancolin; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2016)

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. - Henry Wong; Vaughn Betz; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2016)

Energy efficient object detection on the mobile GP-GPU. - Fitsum Assamnew Andargie; Jonathan Rose; Todd M. Austin; Valeria Bertacco (AFRICON, 2017)

Synchronization Constraints for Interconnect Synthesis. - Alex Rodionov; Jonathan Rose (FPGA, 2017)

Automatic Topology Optimization for FPGA Interconnect Synthesis. - Alex Rodionov; Jonathan Rose (FPL, 2018)

SmartEye: An Accurate Infrared Eye Tracking System for Smartphones. - Braiden Brousseau; Jonathan Rose; Moshe Eizenman (UEMCON, 2018)

High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. - Henry Wong; Vaughn Betz; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2018)

Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning. - Soumil Chugh; Braiden Brousseau; Jonathan Rose; Moshe Eizenman (ICPR, 2020)

Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model. - Braiden Brousseau; Jonathan Rose; Moshe Eizenman (Sensors, 2020)

Optimizing FPGA Logic Block Architectures for Arithmetic. - Kevin E. Murray; Jason Luu; Matthew J. P. Walker; Conor McCullough; Sen Wang; Safeen Huda; Bo Yan; Charles Chiasson; Kenneth B. Kent; Jason Helge Anderson; Jonathan Rose; Vaughn Betz (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. - Andrew Brown; Jiading Zhu; Mohamed Abdelwahab; Alec Dong; Cindy Wang; Jonathan Rose (EACL (1), 2024)

Plug and Play with Prompts: A Prompt Tuning Approach for Controlling Text Generation. - Rohan Deepak Ajwani; Zining Zhu 001; Jonathan Rose; Frank Rudzicz (CoRR, 2024)

A Fully Generative Motivational Interviewing Counsellor Chatbot for Moving Smokers Towards the Decision to Quit. - Zafarullah Mahmood; Soliman Ali; Jiading Zhu; Mohamed Abdelwahab; Michelle Yu Collins; Sihan Chen; Yi Cheng Zhao; Jodi Wolff; Osnat C. Melamed; Nadia Minian; Marta Maslej; Carolynne Cooper; et al. (ACL (Findings), 2025)