An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations. - Jonathan Saul (ICCD, 1991)

State Assignment Algorithms for Parallel Controller Synthesis. - James Pardey; Tomasz Kozlowski; Jonathan Saul; Martin Bolton (ICCD, 1992)

An efficient verification algorithm for parallel controllers. - Krzysztof Bilinski; Erik L. Dagless; Jonathan Saul; Janusz Szajna (EURO-DAC, 1994)

Architecture Oriented Logic Optimization for Lookup Table Based FPGAs. - Aiguo Lu; Jonathan Saul; Erik L. Dagless (ICCD, 1994)

An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions. - Tomasz Kozlowski; Erik L. Dagless; Jonathan Saul (ICCD, 1995)

Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form. - Nigel Lester; Jonathan Saul (FPL, 1996)

Technology mapping of heterogeneous LUT-based FPGAs. - Maurice Kilavuka Inuani; Jonathan Saul (FPL, 1997)

Re-synthesis in technology mapping for heterogeneous FPGAs. - Maurice Kilavuka Inuani; Jonathan Saul (ICCD, 1998)

Hardware/Software Codesign for FPGA-based Systems. - Jonathan Saul (HICSS, 1999)

A High Speed Reconfigurable Firewall Based on Parameterization FPGA-Based Content Addressable Memories. - Alistair McEwan; Jonathan Saul; Andrew Bailey (PDPTA, 1999)

A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories. - Alistair A. McEwan; Jonathan Saul (J. Supercomput., 2001)