A 64-bit MIPS processor running freebsd on a portable FPGA tablet. - Jonathan Woodruff; A. Theodore Markettos; Simon W. Moore (FPL, 2013)

The CHERI capability model: Revisiting RISC in an age of risk. - Jonathan Woodruff; Robert N. M. Watson; David Chisnall; Simon W. Moore; Jonathan Anderson; Brooks Davis; Ben Laurie; Peter G. Neumann; Robert M. Norton; Michael Roe (ISCA, 2014)

CHERI: a RISC capability machine for practical memory safety. - Jonathan Woodruff (2014)

Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine. - David Chisnall; Colin Rothwell; Robert N. M. Watson; Jonathan Woodruff; Munraj Vadera; Simon W. Moore; Michael Roe; Brooks Davis; Peter G. Neumann (ASPLOS, 2015)

CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization. - Robert N. M. Watson; Jonathan Woodruff; Peter G. Neumann; Simon W. Moore; Jonathan Anderson; David Chisnall; Nirav H. Dave; Brooks Davis; Khilan Gudka; Ben Laurie; Steven J. Murdoch; Robert M. Norton; et al. (IEEE Symposium on Security and Privacy, 2015)

Fast Protection-Domain Crossing in the CHERI Capability-System Architecture. - Robert N. M. Watson; Robert M. Norton; Jonathan Woodruff; Simon W. Moore; Peter G. Neumann; Jonathan Anderson; David Chisnall; Brooks Davis; Ben Laurie; Michael Roe; Nirav H. Dave; Khilan Gudka; et al. (IEEE Micro, 2016)

Lane Change and Merge Maneuvers for Connected and Automated Vehicles: A Survey. - David M. Bevly; Xiao Long Cao; Mikhail Gordon; Guchan Ozbilgin; David Kari; Brently Nelson; Jonathan Woodruff; Matthew J. Barth; Chase C. Murray; Arda Kurt; Keith A. Redmill; Ümit Özgüner (IEEE Trans. Intell. Veh., 2016)

CHERI JNI: Sinking the Java Security Model into the C. - David Chisnall; Brooks Davis; Khilan Gudka; David Brazdil; Alexandre Joannou; Jonathan Woodruff; A. Theodore Markettos; J. Edward Maste; Robert M. Norton; Stacey D. Son; Michael Roe; Simon W. Moore; et al. (ASPLOS, 2017)

Efficient Tagged Memory. - Alexandre Joannou; Jonathan Woodruff; Robert Kovacsics; Simon W. Moore; Alex Bradbury; Hongyan Xia; Robert N. M. Watson; David Chisnall; Michael Roe; Brooks Davis; Edward Napierala; John Baldwin; et al. (ICCD, 2017)

Investigating the Use of a Dynamic Physical Bar Chart for Data Exploration and Presentation. - Faisal Taher; Yvonne Jansen; Jonathan Woodruff; John Hardy; Kasper Hornbæk; Jason Alexander (IEEE Trans. Vis. Comput. Graph., 2017)

CheriRTOS: A Capability Model for Embedded Devices. - Hongyan Xia; Jonathan Woodruff; Hadrien Barral; Lawrence Esswood; Alexandre Joannou; Robert Kovacsics; David Chisnall; Michael Roe; Brooks Davis; Edward Napierala; John Baldwin; Khilan Gudka; et al. (ICCD, 2018)

CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. - Brooks Davis; Robert N. M. Watson; Alexander Richardson 001; Peter G. Neumann; Simon W. Moore; John Baldwin; David Chisnall; Jessica Clarke 001; Nathaniel Wesley Filardo; Khilan Gudka; Alexandre Joannou; Ben Laurie; et al. (ASPLOS, 2019)

CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. - Hongyan Xia; Jonathan Woodruff; Sam Ainsworth; Nathaniel Wesley Filardo; Michael Roe; Alexander Richardson 001; Peter Rugg; Peter G. Neumann; Simon W. Moore; Robert N. M. Watson; Timothy M. Jones 001 (MICRO, 2019)

Data transfer: A longitudinal analysis of clipboard and drag-and-drop use in desktop applications. - Jonathan Woodruff; Jason Alexander (Int. J. Hum. Comput. Stud., 2019)

CHERI Concentrate: Practical Compressed Capabilities. - Jonathan Woodruff; Alexandre Joannou; Hongyan Xia; Anthony C. J. Fox; Robert M. Norton; David Chisnall; Brooks Davis; Khilan Gudka; Nathaniel Wesley Filardo; A. Theodore Markettos; Michael Roe; Peter G. Neumann; et al. (IEEE Trans. Computers, 2019)

Cornucopia: Temporal Safety for CHERI Heaps. - Nathaniel Wesley Filardo; Brett F. Gutstein; Jonathan Woodruff; Sam Ainsworth; Lucian Paul-Trifu; Brooks Davis; Hongyan Xia; Edward Tomasz Napierala; Alexander Richardson 001; John Baldwin; David Chisnall; Jessica Clarke 001; et al. (SP, 2020)

Architectural Contracts for Safe Speculation. - Franz A. Fuchs; Jonathan Woodruff; Peter Rugg; Marno van der Maas; Alexandre Joannou; Alexander Richardson 001; Jessica Clarke 001; Nathaniel Wesley Filardo; Brooks Davis; John Baldwin; Peter G. Neumann; Simon W. Moore; et al. (ICCD, 2023)

Towards xBGAS on CHERI: Supporting a Secure Global Memory. - Mert Side; Brody Williams; John D. Leidel; Jonathan Woodruff; Simon W. Moore; Yong Chen 001 (IPDPS Workshops, 2023)

The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System. - Richard Grisenthwaite; Graeme Barnes; Robert N. M. Watson; Simon W. Moore; Peter Sewell; Jonathan Woodruff (IEEE Micro, 2023)

Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety. - Nathaniel Wesley Filardo; Brett F. Gutstein; Jonathan Woodruff; Jessica Clarke 001; Peter Rugg; Brooks Davis; Mark Johnston; Robert M. Norton; David Chisnall; Simon W. Moore; Peter G. Neumann; Robert N. M. Watson (ASPLOS (2), 2024)

A Suite of Processors to Explore CHERI-RISC-V Micro Architecture. - Peter Rugg; Jonathan Woodruff; Alexandre Joannou; Simon W. Moore (DSD, 2024)

Safe Speculation for Cheri. - Franz A. Fuchs; Jonathan Woodruff; Peter Rugg; Alexandre Joannou; Jessica Clarke 001; John Baldwin; Brooks Davis; Peter G. Neumann; Robert N. M. Watson; Simon W. Moore (ICCD, 2024)

CHERI: Hardware-Enabled C/C++ Memory Protection at Scale. - Robert N. M. Watson; David Chisnall; Jessica Clarke 001; Brooks Davis; Nathaniel Wesley Filardo; Ben Laurie; Simon W. Moore; Peter G. Neumann; Alexander Richardson 001; Peter Sewell; Konrad Witaszczyk; Jonathan Woodruff (IEEE Secur. Priv., 2024)

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. - Alexandre Joannou; Peter Rugg; Jonathan Woodruff; Franz A. Fuchs; Marno van der Maas; Matthew Naylor; Michael Roe; Robert N. M. Watson; Peter G. Neumann; Simon W. Moore (IEEE Des. Test, 2024)