A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. - Ji-Hoon Lim; Jong-Chan Ha; Won-Young Jung; Yong-Ju Kim; Jae-Kyung Wee (IEICE Trans. Electron., 2007)

A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. - Young San Shin; Jae-Kyung Wee; Jong-Chan Ha; Ji-Hoon Lim; Yong-Ju Kim; Young-Sang Son (J. Circuits Syst. Comput., 2011)