A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM. - Jong-Chern Lee; Sin-Hyun Jin; Dae-Suk Kim; Young Jun Ku; Chul Kim; Byung-Kwon Park; Hong-Gyeom Kim; Seong-Jun Ahn; Jaejin Lee; Sung-Joo Hong (A-SSCC, 2011)

High bandwidth memory(HBM) with TSV technique. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Sangmuk Oh; Hyun Sung Lee; Ki Hun Kwon; et al. (ISOCC, 2016)

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Yeon Ok Kim; Jae-Hwan Kim; Jin Ho Kim; et al. (ISSCC, 2016)

High-Bandwidth Memory (HBM) Test Challenges and Solutions. - Hongshin Jun; Sang Kyun Nam; Han Ho Jin; Jong-Chern Lee; Yong Jae Park; Jaejin Lee (IEEE Des. Test, 2017)