Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. - Woo Young Choi; Jong Duk Lee; Byung-Gook Park (ISLPED, 2003)

Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. - Ki-Whan Song; Sang-Hoon Lee; Dae Hwan Kim; Kyung Rok Kim; Jaewoo Kyung; Gwanghyeon Baek; Chun-An Lee; Jong Duk Lee; Byung-Gook Park (ISMVL, 2003)

Synchronous mirror delay for multiphase locking. - Yong-Jin Yoon; Hyuck In Kwon; Jong Duk Lee; Byung Gook Park; Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (IEEE J. Solid State Circuits, 2004)

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements. - Hyuck In Kwon; In Man Kang; Byung-Gook Park; Jong Duk Lee; Sang Sik Park; Jung Chak Ahn; Yong Hee Lee (Microelectron. Reliab., 2004)

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. - Seongjae Cho; Jang-Gn Yun; Il-Han Park; Jung Hoon Lee; Jong Pil Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2007)

Design and Simulation of Asymmetric MOSFETs. - Jong Pil Kim; Woo Young Choi; Jae Young Song; Seongjae Cho; Sang Wan Kim; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2007)

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). - Seongjae Cho; Il-Han Park; Jung Hoon Lee; Jang-Gn Yun; Doo-Hyun Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2008)

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. - Jang-Gn Yun; Il-Han Park; Seongjae Cho; Jung Hoon Lee; Doo-Hyun Kim; Gil Sung Lee; Yoon Kim; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2008)

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). - Seongjae Cho; Jung Hoon Lee; Gil Sung Lee; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design. - Jongwook Jeon; Ickhyun Song; Jong Duk Lee; Byung-Gook Park; Hyungcheol Shin (IEICE Trans. Electron., 2009)

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. - Yoon Kim; Seongjae Cho; Gil Sung Lee; Il-Han Park; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. - Doo-Hyun Kim; Il-Han Park; Seongjae Cho; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. - Sang Hyuk Park; Sangwoo Kang; Seongjae Cho; Dong-Seup Lee; Jung Han Lee; Hong-Seon Yang; Kwon-Chil Kang; Joung-Eob Lee; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2009)