A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. - Hyun-Woo Lee; Soo-Bin Lim; Junyoung Song; Jabeom Koo; Dae-Han Kwon; Jong-Ho Kang; Yunsaing Kim; Young-Jung Choi; Kunwoo Park; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2012)

A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. - Kyu-Nam Lim; Woong-Ju Jang; Hyung-Sik Won; Kang-Yeol Lee; Hyungsoo Kim; Dong-Whee Kim; Mi-Hyun Cho; Seung-Lo Kim; Jong-Ho Kang; Keun-Woo Park; Byung-Tae Jeong (ISSCC, 2012)

A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel. - Hyunbae Lee; Taeksang Song; Sangyeon Byeon; Kwanghun Lee; Inhwa Jung; Seongjin Kang; Ohkyu Kwon; Koeun Cheon; Donghwan Seol; Jong-Ho Kang; Gunwoo Park; Yunsaing Kim (A-SSCC, 2014)

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. - Ji-Wook Kwon; Dong-Hwan Jin; Hyeon-June Kim; Sun-Il Hwang; Min-Chul Shin; Jong-Ho Kang; Seung-Tak Ryu (CICC, 2014)

Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology. - Junho Cheon; Insoo Lee; Changyong Ahn; Milos Stanisavljevic; Aravinthan Athmanathan; Nikolaos Papandreou; Haris Pozidis; Evangelos Eleftheriou; Min-Chul Shin; Taekseung Kim; Jong-Ho Kang; Jun Hyun Chun (CICC, 2015)

Design considerations of HBM stacked DRAM and the memory architecture extension. - Dong-Uk Lee; Kang Seol Lee; Yongwoo Lee; Kyung Whan Kim; Jong-Ho Kang; Jaejin Lee; Jun Hyun Chun (CICC, 2015)

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel. - Hyunbae Lee; Taeksang Song; Sangyeon Byeon; Kwanghun Lee; Inhwa Jung; Seongjin Kang; Ohkyu Kwon; Koeun Cheon; Donghwan Seol; Jong-Ho Kang; Gunwoo Park; Yunsaing Kim (IEEE J. Solid State Circuits, 2015)