On reordering instruction streams for pipelined computers. - Jong-Jiann Shieh; Christos A. Papachristou (MICRO, 1989)

An instruction reoderer for pipelined computers. - Jong-Jiann Shieh; Christos A. Papachristou (MICRO, 1990)

A Multiple Blocks Fetch Engine for High Performance Superscalar Processors. - Yung-Chung Wu; Jong-Jiann Shieh (PDCS, 2001)

Block Based Fetch Engine for Superscalar Processors. - Zheng-Kuo Wu; Jong-Jiann Shieh (CAINE, 2002)

An Issue Logic for Superscalar Microprocessors. - Feng-Jiann Shiao; Jong-Jiann Shieh (CAINE, 2003)

Dynamic Fetch Engine for Simultaneous Multithreaded Processors. - Tzung-Rei Yang; Jong-Jiann Shieh (Asia-Pacific Computer Systems Architecture Conference, 2004)

Speculative Issue Logic. - You-Jan Tsai; Jong-Jiann Shieh (Asia-Pacific Computer Systems Architecture Conference, 2005)

Power Improvement Using Block-Based Loop Buffer with Innermost Loop Control. - Ming-Yuan Zhong; Jong-Jiann Shieh (ICA3PP (2), 2010)