A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits. - Jae-Young Park; Jong-Kyu Song; Chang-Soo Jang; San-Hong Kim; Won-Young Jung; Taek-Soo Kim (IEICE Trans. Electron., 2009)

Analysis and modeling of a Low Voltage Triggered SCR ESD protection clamp with the very fast Transmission Line Pulse measurement. - Jae-Young Park; Jong-Kyu Song; Chang-Soo Jang; Young-Sang Son; Dae-Woo Kim (ISQED, 2010)

On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs. - Jae-Young Park; Jong-Kyu Song; Dae-Woo Kim; Chang-Soo Jang; Won-Young Jung; Taek-Soo Kim (IEICE Trans. Electron., 2010)

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process. - Jae-Young Park; Dae-Woo Kim; Young-Sang Son; Jong-Kyu Song; Chang-Soo Jang; Won-Young Jung (IEICE Trans. Electron., 2011)