Improving SiC lateral DMOSFET reliability under high field stress. - Tesfaye Ayalew; Andreas Gehring; Jong Mun Park; Tibor Grasser; Siegfried Selberherr (Microelectron. Reliab., 2003)

High-voltage lateral trench gate SOI-LDMOSFETs. - Jong Mun Park; Robert Klima; Siegfried Selberherr (Microelectron. J., 2004)

A method for generating structurally aligned grids for semiconductor device simulation. - Clemens Heitzinger; Alireza Sheikholeslami; Jong Mun Park; Siegfried Selberherr (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Evolution of a CMOS Based Lateral High Voltage Technology Concept. - Martin Knaipp; Jong Mun Park; Verena Vescoli (Microelectron. J., 2006)

Analysis of hot carrier effects in a 0.35 µm high voltage n-channel LDMOS transistor. - Hubert Enichlmair; Sara Carniello; Jong Mun Park; Rainer Minixhofer (Microelectron. Reliab., 2007)

Hot-carrier reliability in high-voltage lateral double-diffused MOS transistors. - Verena Vescoli; Jong Mun Park; Hubert Enichlmair; Martin Knaipp; Georg Röhrer; Rainer Minixhofer; Martin Schrems (IET Circuits Devices Syst., 2008)

Interface traps density-of-states as a vital component for hot-carrier degradation modeling. - Stanislav Tyaginov; Ivan A. Starkov; Oliver Triebl; Johann Cervenka; C. Jungemann; Sara Carniello; Jong Mun Park; Hubert Enichlmair; Markus Karner; Ch. Kernstock; Ehrenfried Seebacher; Rainer Minixhofer; et al. (Microelectron. Reliab., 2010)

An analytical approach for physical modeling of hot-carrier induced degradation. - Stanislav Tyaginov; Ivan A. Starkov; Hubert Enichlmair; C. Jungemann; Jong Mun Park; Ehrenfried Seebacher; R. L. de Orio; Hajdin Ceric; Tibor Grasser (Microelectron. Reliab., 2011)

Optical sensor process variability in a 0.18 μm high voltage CMOS technology. - Frederic Roger; Anderson Pires Singulani; Jong Mun Park (PATMOS, 2017)