A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. - Hae-Kang Jung; Kyoungho Lee; Jong-Sam Kim; Jae-Jin Lee; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2009)

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. - Hyun-Woo Lee; Hoon Choi; Beom-Ju Shin; Kyung-Hoon Kim; Kyung Whan Kim; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Jae-Hwan Kim; Eun Young Park; Jong-Sam Kim; Jong-Hwan Kim; et al. (IEEE J. Solid State Circuits, 2012)

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. - Soo-Min Lee; Jong-Hoon Kim; Jong-Sam Kim; Yunsaing Kim; Hyunbae Lee; Jae-Yoon Sim; Hong-June Park (ISSCC, 2013)

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. - Dongkyun Kim; Minsu Park; Sungchun Jang; Jun-Yong Song; Hankyu Chi; Geunho Choi; Sunmyung Choi; Jaeil Kim; Changhyun Kim; Kyung Whan Kim; Kibong Koo; Seonghwi Song; et al. (ISSCC, 2019)

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. - Dongkyun Kim; Kibong Koo; Yongmi Kim; Dong-Uk Lee; Jaejin Lee; Ki Hun Kwon; Byeongchan Choi; Hongjung Kim; Sanghyun Ku; Jong-Sam Kim; Seungwook Oh; Minsu Park; et al. (IEEE J. Solid State Circuits, 2020)