13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2014)

A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Yongho Kim; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; et al. (IEEE J. Solid State Circuits, 2015)

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Jonghoon Jung; Giyong Yang; Sanghoon Baek; Jaeseung Choi 001; Bongjae Kwon; Yunwoo Lee; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2016)

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Giyong Yang; Hoonki Kim; Sanghoon Baek; Jonghoon Jung; Bongjae Kwon; Sungwee Cho; Hyuntaek Jung; Yongjae Choo; et al. (IEEE J. Solid State Circuits, 2017)

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. - Taejoong Song; Jonghoon Jung; Woojin Rim; Hoonki Kim; Yongho Kim; Changnam Park; Jeongho Do; Sunghyun Park 003; Sungwee Cho; Hyuntaek Jung; Bongjae Kwon; Hyun-Su Choi; et al. (ISSCC, 2018)

24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Woojin Rim; Hoonki Kim; Keun Hwi Cho; Taeyeong Kim; Taejung Lee; Geumjong Bae; Dong-Won Kim; S. D. Kwon; Sanghoon Baek; Jonghoon Jung; Jongwook Kye; et al. (ISSCC, 2021)

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. - Taejoong Song; Hakchul Jung; Giyoung Yang; Hoyoung Tang; Hayoung Kim; Dongwook Seo; Hoonki Kim; Woojin Rim; Sanghoon Baek; Sangyeop Baeck; Jonghoon Jung (CICC, 2022)

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. - Giyoung Yang; Hakchul Jung; Jinyoung Lim; Jaewoo Seo; Ingyum Kim; Jisu Yu; Hyeoungyu You; Jeongsoon Kong; Garoom Kim; Minjae Jeong; Chanhee Park; Sera An; et al. (VLSI Technology and Circuits, 2022)

A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Hoonki Kim; Woojin Rim; Hakchul Jung; Changnam Park; Inhak Lee; Sanghoon Baek; Jonghoon Jung (IEEE J. Solid State Circuits, 2022)