An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS. - JongHyun Ko; KwanWoo Park; Suhyeong Yong; TaeGam Jeong; Taehak Kim; Taigon Song (ISMVL, 2021)

A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node. - Jaehoon Jeong; JongHyun Ko; Taigon Song (ISLPED, 2022)

Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design. - JongHyun Ko; Jongbeom Kim; TaeGam Jeong; Jaehoon Jeong; Taigon Song (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

T3L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure. - Jongbeom Kim; Hyundong Lee; JongHyun Ko; Bongjun Kim; Taigon Song (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node. - Jaehoon Jeong; Yunjeong Shin; Hyundong Lee; JongHyun Ko; Jongbeom Kim; Taigon Song (IEEE Access, 2024)

SNNSim: Investigation and Optimization of Large-Scale Analog Spiking Neural Networks Based on Flash Memory Devices. - JongHyun Ko; Dongseok Kwon; Joon Hwang; Kyu-Ho Lee; Seongbin Oh; Jeonghyun Kim; Jiseong Im; Ryun-Han Koo; Jae-Joon Kim; Jong-Ho Lee 002 (Adv. Intell. Syst., 2024)

NeuroTorch: DRAM-free nonvolatile memory-based hybrid training compute-in-memory system simulator. - JongHyun Ko; Inseok Lee; Kyu-Ho Lee; Joon Hwang; Min-Kyu Park; Jiseong Im; Jeonghyun Kim; Ryun-Han Koo; Sung-Ho Park; Jae-Joon Kim; Jong-Ho Lee (Neurocomputing, 2025)

Vertical NAND flash memory-based matrix-matrix multiplication scheme for energy-efficient attention score computation. - JongHyun Ko; Sung-Ho Park; Jiseong Im; Jeonghyun Kim; Ryun-Han Koo; Yeongheon Yang; Jong-Ho Lee (Neurocomputing, 2025)