A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. - Jongshin Shin; Jaehyun Park; Bongjin Kim; Jongjae Ryu; Chiwon Kim; Jiyoung Kim; Seung-Hee Yang; Hyungoo Kim; Jaewhui Kim (CICC, 2008)

A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology. - Subhadeep Datta; Arnab Banerjee; Ayush Tripathi; Dongmin Kang; Leesunghyuck; Hasung Lim; Wonsik Yu; Kgj Vishnu; Chanyoung Jeong; Sumanth Chakkirala; Avneesh Singh Verma; Sachin Kashyap; et al. (A-SSCC, 2024)