A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier. - Yunjae Suh; Jongmi Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

5.7 A 29nW bandgap reference circuit. - Jongmi Lee; Youngwoo Ji; Seungnam Choi; Young-Chul Cho; Seong-Jin Jang; Joo-Sun Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2015)

A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS. - Jongmi Lee; Jongwoo Lee; Chilun Lo; Jaehoon Lee 005; In-Young Lee; Byungki Han; Seunghyun Oh; Thomas Byunghak Cho (A-SSCC, 2017)

30.2 NB-IoT and GNSS All-in-One System-on-Chip Integrating RF Transceiver, 23dBm CMOS Power Amplifier, Power Management Unit and Clock Management System for Low-Cost Solution. - Jongsoo Lee; Jae-Yeol Han; Chilun Lo; Jongmi Lee; Wan Kim; Seungjin Kim; Byoungjoong Kang; Juyoung Han; Sangdon Jung; Takahiro Nomiyama; Jongwoo Lee; Thomas Byunghak Cho; et al. (ISSCC, 2020)

NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution. - Jongsoo Lee; Jae-Yeol Han; Chilun Lo; Jongmi Lee; Wan Kim; Seungjin Kim; Byoungjoong Kang; Juyoung Han; Sangdon Jung; Takahiro Nomiyama; Jongwoo Lee; Thomas Byunghak Cho; et al. (IEEE J. Solid State Circuits, 2020)

10.1 A 116μ W 104.4dB-DR 100.6dB-SNDR CT Δ∑ Audio ADC Using Tri-Level Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter. - Chilun Lo; Jongmi Lee; Yong Lim; Younghyun Yoon; Hyunseok Hwang; Jaehoon Lee 005; Moo-Yeol Choi; Myungjin Lee; Seunghyun Oh; Jongwoo Lee (ISSCC, 2021)

A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET. - Jaehoon Lee 005; Yong Lim; Jongmi Lee; Taejin Jang; Kwonwoo Kang; Jongpil Cho; Seunghyun Oh; Jongwoo Lee (VLSI Technology and Circuits, 2022)

9.6 A 6th-Order Quadrature CTDSM using Double-OTA and Quadrature NSSAR with 171.3dB FoMs in 14nm. - Jongmi Lee; Seong-Eun Cho; Jaehoon Lee 005; Yong Lim; Seunghyun Oh; Jongwoo Lee; Sung-Ung Kwak (ISSCC, 2024)

9.2 A 2.08mW 64.4dB SNDR 400MS/s 12b Pipelined-SAR ADC using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8nm. - Yong Lim; Jaehoon Lee 005; Jongmi Lee; Kwangmin Lim; Seunghyun Oh; Jongwoo Lee; Sung-Ung Kwak (ISSCC, 2024)

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm. - Yong Lim; Jaehoon Lee 005; Jongmi Lee; Kwangmin Lim; Seunghyun Oh; Jongwoo Lee (IEEE J. Solid State Circuits, 2024)