An energy-delay efficient 2-level data cache architecture for embedded system. - Jongmin Lee 002; Soontae Kim (ISLPED, 2009)

Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system. - Soontae Kim; Jongmin Lee 002 (ACM Great Lakes Symposium on VLSI, 2010)

TLB index-based tagging for cache energy reduction. - Jongmin Lee 002; Seokin Hong; Soontae Kim (ISLPED, 2011)

Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. - Soontae Kim; Jongmin Lee 002; Jesung Kim; Seokin Hong (MICRO, 2011)

Adopting TLB index-based tagging to data caches for tag energy reduction. - Jongmin Lee 002; Soontae Kim (ISLPED, 2012)

Skinflint DRAM system: Minimizing DRAM chip writes for low power. - Yebin Lee; Soontae Kim; Seokin Hong; Jongmin Lee 002 (HPCA, 2013)

Ternary cache: Three-valued MLC STT-RAM caches. - Seokin Hong; Jongmin Lee 002; Soontae Kim (ICCD, 2014)

Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction. - Jongmin Lee 002; Soontae Kim (IEEE Trans. Computers, 2015)

Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems. - Jongmin Lee 002; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption. - Jesung Kim; Jongmin Lee 002; Soontae Kim (IEEE Trans. Computers, 2017)

A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption. - Jungwoo Park; Jongmin Lee 002; Soontae Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)