Process variation tolerant all-digital multiphase DLL for DDR3 interface. - Heechai Kang; Kyungho Ryu; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (CICC, 2010)

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. - Heechai Kang; Kyungho Ryu; Dong-Hoon Jung; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. - Kwanyeob Chae; JongRyun Choi; Shinyoung Yi 002; Won Lee; Sanghoon Joo; Hyunhyuck Kim; Hyungkwon Yi; Yoonjee Nam; Jinho Choi; Sanghune Park; Sanghyun Lee (ESSCIRC, 2016)

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. - Soo-Min Lee; Jihun Oh; Jinho Choi; Seokkyun Ko; Daero Kim; Kyounghoi Koo; JongRyun Choi; Yoonjee Nam; Sangsoo Park; Hyungkweon Lee; Eunsu Kim; Sukhyun Jung; et al. (ISSCC, 2017)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)