A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. - Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim (CICC, 1999)

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. - Yongsam Moon; Jongsang Choi; Kyeongho Lee; Deog-Kyoon Jeong; Min-Kyu Kim (IEEE J. Solid State Circuits, 2000)