A new charge pump without degradation in threshold voltage due to body effect [memory applications]. - Jongshin Shin; In-Young Chung; Young June Park; Hong-Shick Min (IEEE J. Solid State Circuits, 2000)

A genetic approach to automatic bias generation for biased random instruction generation. - Mrinal Bose; Jongshin Shin; Elizabeth M. Rudnick; Todd Dukes; Magdy Abadir (CEC, 2001)

At-speed logic BIST using a frozen clock testing strategy. - Jongshin Shin; Xiaoming Yu; Elizabeth M. Rudnick; Miron Abramovici (ITC, 2001)

A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA. - Jongshin Shin; Ilwon Seo; Jiyoung Kim; Seung-Hee Yang; Chiwon Kim; Jaehyun Park; Hyungoo Kim; Myoungbo Kwak; GhyBoong Hong (CICC, 2006)

A 65nm 3.4Gbps HDMI TX PHY with supply-regulated dual-tuning PLL and blending multiplexer. - Jongshin Shin; Jaehyun Park; Bongjin Kim; Jongjae Ryu; Chiwon Kim; Jiyoung Kim; Seung-Hee Yang; Hyungoo Kim; Jaewhui Kim (CICC, 2008)

New charge pump circuits for high output voltage and large current drivability. - In-Young Chung; Jongshin Shin (IEICE Electron. Express, 2009)

A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance. - June-Hee Lee; Sang-Hoon Kim; Jongshin Shin; Dong-Chul Choi; Kee-Won Kwon; Jung-Hoon Chun (MWSCAS, 2013)

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization. - Seungnam Choi; Hyunwoo Son; Jongshin Shin; Sang-Hyun Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. - Kwanyeob Chae; Billy Koo; Jihun Oh; Sanghune Park; Jongshin Shin; Jaehong Park (ISOCC, 2018)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)

11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries. - Min-Woo Ko; Gyeong-Gu Kang; Ki-Duk Kim; Ji-Hun Lee; Seok-Tae Koh; Tae-Hwang Kong; Sang-Ho Kim; Sungyong Lee; Michael Choi; Jongshin Shin; Gyu-Hyeong Cho; Hyunsik Kim (ISSCC, 2020)

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. - Soo-Min Lee; Kihwan Seong; Joohee Shin; Hyoungjoong Kim; Jaehyun Jeong; Shinyoung Yi 002; Juyoung Kim; Eunsu Kim; Sukhyun Jung; Sangyun Hwang; Jihun Oh; Kwanyeob Chae; et al. (ISSCC, 2020)

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. - Byoung-Joo Yoo; Dong-Hyuk Lim; Hyonguk Pang; June-Hee Lee; Seung-Yeob Baek 002; Naxin Kim; Dong-Ho Choi; Young-Ho Choi; Hyeyeon Yang; Taehun Yoon; Sang-Hyeok Chu; Kangjik Kim; et al. (ISSCC, 2020)

A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS. - Changzhi Yu; Euije Sa; Soowan Jin; Himchan Park; Jongshin Shin; Jinwook Burm (IEEE J. Solid State Circuits, 2020)

An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss. - Cheolmin Ahn; Jaehyeong Hong; Jongshin Shin; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst., 2020)

Samsung Physically Unclonable Function (SAMPUF™) and its integration with Samsung Security System. - Yongki Lee; Bohdan Karpinskyy; Yunhyeok Choi; Kyoung-Moon Ahn; Yongsoo Kim; Jieun Park; Sumin Noh; Jisu Kang; Jonghoon Shin; Jaechul Park; Youngjin Chung; Jongshin Shin (CICC, 2021)

A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. - Seung-Yeob Baek 002; Il-Hoon Jang; Michael Choi; Hyungdong Roh; Woongtaek Lim; Youngjae Cho; Jongshin Shin (ISSCC, 2021)

29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS. - Dong-Hoon Jung; Tae-Hwang Kong; Jun-Hyeok Yang; SangHo Kim; Kwangho Kim; Jeongpyo Park; Michael Choi; Jongshin Shin (ISSCC, 2021)

A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor. - Woojoong Jung; Minsu Kim; Hyunjun Park; Sungmin Yoo; Tae-Hwang Kong; Jun-Hyeok Yang; Michael Choi; Jongshin Shin; Hyung-Min Lee (CICC, 2022)

Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. - Dokyung Lim; Sounghun Shin; Seungmin Lee; Kihyun Kwon; Jeongmin An; Wonsik Yu; Chanyoung Jeong; WooSeok Kim; Michael Choi; Jongshin Shin (ISSCC, 2022)

A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS. - Junghyun Park; Jooseong Kim; Kwangho Kim; Jun-Hyeok Yang; Michael Choi; Jongshin Shin (ISSCC, 2022)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. - Byeongwoo Koo; Sunghan Do; Sang-Pil Nam; Heewook Shin; Sungno Lee; Eunhye Oh; Jaemin Hong; Jung-Ho Lee; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)

An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. - Kyung-Hoon Lee; Jinwoo Park; Younghyo Park; Byeongwoo Koo; Sunghan Do; Woongtaek Lim; Sungno Lee; Hyochul Shin; Eunhye Oh; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. - Kyoung-Jun Moon; Dong-Ryeol Oh; Young-Hyo Park; Kyung-Hoon Lee; Sun-Jae Park; Sung-No Lee; Hee-Chang Hwang; Hyo-Chul Shin; Young-Jae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. - Jusung Lee; Youngwoo Jo; Wonsik Yu; WooSeok Kim; Michael Choi; Sanghune Park; Jongshin Shin (CICC, 2023)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. - Kihwan Seong; Donguk Park; Gyeom-Je Bae; Hyunwoo Lee; Youngseob Suh; Wooseuk Oh; Hyemun Lee; Juyoung Kim; Takgun Lee; Geonhoo Mo; Sukhyun Jung; Dongcheol Choi; et al. (ISSCC, 2023)

Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor. - Jaehoon Jeong; Hyungeun Kim; Jaehyun Park; Jongshin Shin; Jinho Jeong 001 (IEEE Access, 2023)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM. - Yoonjae Choi; Jaegeun Song; Daero Kim; Myunggon Kim; Jiyeon Park; Jinho Choi; Changki Kwon; Minho Seo; Jihun Oh; Shinyoung Yi 002; Billy Koo; Kwanyeob Chae; et al. (A-SSCC, 2024)

3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor. - Sangheon Lee; Jinwoo Park; Junsang Park; Sangkyu Lee; Jungho Lee; Youngjae Cho; Michael Choi; Jongshin Shin (ISSCC, 2024)

16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm. - Jieun Park; Yong Ki Lee; Bohdan Karpinskyy; Yunhyeok Choi; Jonghoon Shin; Hyo-Gyuem Rhew; Jongshin Shin (ISSCC, 2024)

13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets. - Kihwan Seong; Wooseuk Oh; Hyunwoo Lee; Gyeom-Je Bae; Youngseob Suh; Hyemun Lee; Juyoung Kim; Eunsu Kim; Yeongeon Kang; Gunhu Mo; Youjin Lee; Mingyeong Kim; et al. (ISSCC, 2024)

A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. - Byeongwoo Koo; Sunghan Do; Sangkyu Lee; Sang-Pil Nam; Heewook Shin; Saemin Im; Hyochul Shin; Sungno Lee; Junsang Park; Jungho Lee; Youngjae Cho; Michael Choi; et al. (VLSI Technology and Circuits, 2024)

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. - Junsang Park; Jinwoo Park; Jaemin Hong; Sun-Jae Park; Dongsuk Lee; Sungno Lee; Hyochul Shin; Kyung-Hoon Lee; Byeongwoo Koo; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2024)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)

Bandwidth Extension of CMOS Amplifier Using Mutually Coupled Three-Inductor Coil. - Hyungeun Kim; Jaehyun Park; Jongshin Shin; Jinho Jeong 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies. - Bohdan Karpinskyy; Yong Ki Lee; Sumin Noh; Yunhyeok Choi; Jieun Park; Jisu Kang; Taewook Park; Eunhye Oh; Gapkyung Kim; Sungha Lee; Hyunwoo Ko; Jonghoon Shin; et al. (ISSCC, 2025)

Bandwidth Extension of Resistive-Feedback CMOS Inverter Amplifier Using T-Coil Peaking. - Minkyung Choi; Hyungeun Kim; Jaehyun Park; Jongshin Shin; Jinho Jeong 001 (IEEE Access, 2025)