Face Recognition Based on ICA Combined with FLD. - Juneho Yi; Jongsun Kim; Jongmoo Choi; JungHyun Han; Eunseok Lee 001 (Biometric Authentication, 2002)

A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability. - Jongsun Kim; Zhiwei Xu 003; M. Frank Chang (CICC, 2003)

Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers. - Jongsun Kim; Zhiwei Xu 003; Mau-Chung Frank Chang (ISCAS (2), 2003)

Robust Skin Color Segmentation Using a 2D Plane of RGB Color Space. - Juneho Yi; Jiyoung Park; Jongsun Kim; Jongmoo Choi (ISCIS, 2003)

A low power capacitive coupled bus interface based on pulsed signaling. - Jongsun Kim; Jung-Hwan Choi; Changhyun Kim; A. F. Chang; Ingrid Verbauwhede (CICC, 2004)

Face Recognition Based on Locally Salient ICA Information. - Jongsun Kim; Jongmoo Choi; Juneho Yi (ECCV Workshop BioAW, 2004)

ICA Based Face Recognition Robust to Partial Occlusions and Local Distortions. - Jongsun Kim; Jongmoo Choi; Juneho Yi (ICBA, 2004)

Robust Face Recognition Based on Part-Based Localized Basis Images. - Jongsun Kim; Juneho Yi (ICIAP, 2005)

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus. - Jongsun Kim; Ingrid Verbauwhede; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2005)

Effective Representation Using ICA for Face Recognition Robust to Local Distortion and Partial Occlusion. - Jongsun Kim; Jongmoo Choi; Juneho Yi; Matthew Turk 001 (IEEE Trans. Pattern Anal. Mach. Intell., 2005)

A Changeable Biometric System That Uses Parts-Based Localized Representation for Face Recognition. - Jongsun Kim; Chulhan Lee; Jaihie Kim (AutoID, 2007)

Changeable Face Representations Suitable for Human Recognition. - Hyung Gu Lee; Chulhan Lee; Jeung-Yoon Choi; Jongsun Kim; Jaihie Kim (ICB, 2007)

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication. - Jongsun Kim; Ingrid Verbauwhede; M.-C. Frank Chang (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems. - Jongsun Kim; Bo-Cheng Lai; Mau-Chung Frank Chang; Ingrid Verbauwhede (IEEE Trans. Computers, 2008)

Area-efficient digitally controlled CMOS feedback delay element with programmable duty cycle. - Jongsun Kim (IEICE Electron. Express, 2009)

A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs. - Hojung Ju; Jongsun Kim (IEICE Electron. Express, 2010)

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. - Gyungsu Byun; Yanghyo Kim; Jongsun Kim; Sai-Wang Tam; Hsieh-Hung Hsieh; P.-Y. Wu; Chewnpu Jou; Jason Cong; Glenn Reinman; Mau-Chung Frank Chang (ISSCC, 2011)

A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects. - Jongsun Kim; Gyungsu Byun; M. Frank Chang (IEICE Trans. Electron., 2011)

Double edge trailing PWM based full digital audio amplifier design. - Seo Weon Heo; Jongsun Kim (ICCE, 2012)

A programmable delay-locked loop based clock multiplier. - Sungken Lee; Geontae Park; Hyungtak Kim; Jongsun Kim (ISOCC, 2012)

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling. - Gyungsu Byun; Yanghyo Kim; Jongsun Kim; Sai-Wang Tam; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2012)

A fast-locking clock multiplying DLL. - Jongsun Kim; Bongho Bae (ISOCC, 2016)

A MDLL-based multi-phase clock multiplier. - Junsub Yoon; Jongsun Kim (ISOCC, 2016)

A low-power SerDes for high-speed on-chip networks. - Dongjun Park; Junsub Yoon; Jongsun Kim (ISOCC, 2017)

A 0.15 to 2.2 GHz all-digital delay-locked loop. - Dongjun Park; Geontae Park; Jongsun Kim (NEWCAS, 2017)

A 2-4 GHz fast-locking frequency multiplying delay-locked loop. - Jongsun Kim; Bongho Bae (IEICE Electron. Express, 2017)

A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs. - Junsub Yoon; Seo Weon Heo; Jongsun Kim (IEICE Electron. Express, 2017)

A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs. - Dongjun Park; Jongsun Kim (ISCAS, 2018)

An anti-harmonic MDLL for phase-aligned on-chip clock multiplication. - Jongsun Kim; B. H. Bae (IEICE Electron. Express, 2018)

A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs. - Jongsun Kim; S. W. Han (IEICE Electron. Express, 2018)

A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling. - Jongsun Kim; Sangwoo Han (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization. - Heejae Hwang; Jongsun Kim (ISOCC, 2019)

A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links. - Heejae Hwang; Jongsun Kim (IEICE Electron. Express, 2019)

An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication. - Taeyeon Kim; Sunguk Choi; S. Han; Jongsun Kim (ISOCC, 2020)

Development of Artificial Neural Network System to Recommend Process Conditions of Injection Molding for Various Geometries. - Chihun Lee; Juwon Na; Kyongho Park; Hyeonjae Yu; Jongsun Kim; Kwonil Choi; Dongyong Park; Seongjin Park; Junsuk Rho; Seungchul Lee (Adv. Intell. Syst., 2020)

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL. - Dongjun Park; Jongsun Kim (Circuits Syst. Signal Process., 2020)

A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication. - Dongjun Park; Jongsun Kim (IEICE Electron. Express, 2020)

A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC. - Taeyeon Kim; Jongsun Kim (ISCAS, 2021)

A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL. - Junghoon Jin; Seungjun Kim; Sunguk Choi; Pil-Ho Lee; Sang-jae Rhee; Ki-hwan Choi; Jongsun Kim (ISOCC, 2021)

A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC. - Chaeyoung Jang; Pil-Ho Lee; Sang-jae Rhee; Ki-hwan Choi; Jongsun Kim (ICEIC, 2022)

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems. - Junghoon Jin; Seungjun Kim; Jongsun Kim (IEEE Access, 2022)

A GaN Driver IC With a TDC-Based Dead-Time Controller For GaN DC-DC Buck Converters. - Yongseung Lee; Donghun Kim; Jongsun Kim (ISOCC, 2023)

A Fast-Lock All-Digital PLL with a TDC-based FLL. - Changhoon Chae; Jongsun Kim (ISOCC, 2024)

A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line. - Taeyeon Kim; Jongsun Kim (Microelectron. J., 2024)