A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (ISSCC, 2023)

The Return of the King: The Importance of Killer Content in a Competitive OTT Market. - Jongwha Kim; Changjun Lee (J. Theor. Appl. Electron. Commer. Res., 2023)

A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces. - Yuhwan Shin; Yongwoo Jo; Juyeop Kim; Junseok Lee; Jongwha Kim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2025)