A low-power dual-path floating-point fused add-subtract unit. - Jae Hong Min; Jongwook Sohn; Earl E. Swartzlander Jr. (ACSCC, 2012)

Improved Architectures for a Fused Floating-Point Add-Subtract Unit. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Improved Architectures for a Floating-Point Fused Dot Product Unit. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Symposium on Computer Arithmetic, 2013)

A Fused Floating-Point Three-Term Adder. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A Fused Floating-Point Four-Term Dot Product Unit. - Jongwook Sohn; Earl E. Swartzlander Jr. (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Enhanced Floating-Point Adder with Full Denormal Support. - Jongwook Sohn; David K. Dean; Eric Quintana; Wing Shek Wong (ARITH, 2022)

Enhanced Floating-Point Multiply-Add with Full Denormal Support. - Jongwook Sohn; David K. Dean; Eric Quintana; Wing Shek Wong (ARITH, 2023)