A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM. - Se Jun Kim; Sang Hoon Hong; Jae-Kyung Wee; Joo-Hwan Cho; Pil Soo Lee; Jin-Hong Ahn; Jin-Yong Chung (IEEE J. Solid State Circuits, 2002)

A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL. - Ki-Won Lee; Joo-Hwan Cho; Byoung-Jin Choi; Geun-Il Lee; Ho-Don Jung; Woo-Young Lee; Ki-Chon Park; Yongsuk Joo; Jaehoon Cha; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn (IEEE J. Solid State Circuits, 2007)

Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster. - Dongsuk Shin; Joo-Hwan Cho; Young-Jung Choi; Byong-Tae Chung (SoCC, 2010)

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. - Dongkyun Kim; Minsu Park; Sungchun Jang; Jun-Yong Song; Hankyu Chi; Geunho Choi; Sunmyung Choi; Jaeil Kim; Changhyun Kim; Kyung Whan Kim; Kibong Koo; Seonghwi Song; et al. (ISSCC, 2019)

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. - Jihyo Kang; Jaehyeok Yang; Kyunghoon Kim; Joo-Hyung Chae; Gang-Sik Lee; Sang-Yeon Byeon; Boram Kim; Dong-Hyun Kim; Youngtaek Kim; Yeongmuk Cho; Junghwan Ji; Sera Jeong; et al. (IEEE J. Solid State Circuits, 2022)

A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. - Soyeong Shin; Yongjae Lee; Jiheon Park; Jihyo Kang; Kyunghoon Kim; Dae-Han Kwon; Sangkwon Lee; Jieun Jang; Joo-Hwan Cho; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)