High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line. - Mino Kim; Woo-Yeol Shin; Gi-Moon Hong; Jihwan Park; Joo-Hyung Chae; Nan Xing; Jong-Kwan Woo; Suhwan Kim 001 (ESSCIRC, 2013)

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. - Joo-Hyung Chae; Gi-Moon Hong; Jihwan Park; Mino Kim; Hyeongjun Ko; Woo-Yeol Shin; Hankyu Chi; Deog-Kyoon Jeong; Suhwan Kim 001 (A-SSCC, 2015)

A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface. - Jihwan Park; Joo-Hyung Chae; Yong-Un Jeong; Jae-Whan Lee; Suhwan Kim 001 (A-SSCC, 2017)

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication. - Jihwan Park; Gi-Moon Hong; Mino Kim; Joo-Hyung Chae; Suhwan Kim 001 (ISLPED, 2017)

An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface. - Minchang Kim; Jihwan Park; Joo-Hyung Chae; Hyeongjun Ko; Mino Kim; Suhwan Kim 001 (ISOCC, 2017)

Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces. - Jae-Whan Lee; Joo-Hyung Chae; Jihwan Park; Hyunkyu Park 002; Jaekwang Yun; Suhwan Kim 001 (ISLPED, 2018)

A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization. - Joo-Hyung Chae; Mino Kim; Gi-Moon Hong; Jihwan Park; Suhwan Kim 001 (IEEE Access, 2018)

A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface. - Jihwan Park; Joo-Hyung Chae; Yong-Un Jeong; Jae-Whan Lee; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2018)

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. - Mino Kim; Joo-Hyung Chae; Sungphil Choi; Gi-Moon Hong; Hyeongjun Ko; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation. - Changho Hyun; Hyeongjun Ko; Joo-Hyung Chae; Hyunkyu Park 002; Suhwan Kim 001 (ISCAS, 2019)

A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. - Yong-Un Jeong; Joo-Hyung Chae; Sungphil Choi; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (ISLPED, 2019)

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner. - Joo-Hyung Chae; Hyeongjun Ko; Jihwan Park; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. - Joo-Hyung Chae; Hyeongjun Ko; Jihwan Park; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces. - Joo-Hyung Chae; Yong-Un Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces. - Joo-Hyung Chae; Minchang Kim; Sungphil Choi; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. - Yong-Un Jeong; Jihwan Park; Mino Kim; Joo-Hyung Chae; Jaekwang Yun; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. - Sangyoon Lee 006; Han-Gon Ko; Joo-Hyung Chae; Soyeong Shin; Jaekwang Yun; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. - Hyunkyu Park 002; Jihwan Park; Jae-Whan Lee; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001; Joo-Hyung Chae (ISCAS, 2021)

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. - Kyunghoon Kim; Joo-Hyung Chae; Jaehyeok Yang; Jihyo Kang; Gang-Sik Lee; Sang-Yeon Byeon; Youngtaek Kim; Boram Kim; Dong-Hyun Kim; Yeongmuk Cho; Kangmoo Choi; Hyeongyeol Park; et al. (ISSCC, 2021)

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. - Sungphil Choi; Yong-Un Jeong; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Access, 2021)

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. - Yong-Un Jeong; Hyunkyu Park 002; Changho Hyun; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2021)

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. - Hyeongjun Ko; Mino Kim; Hyunkyu Park 002; Sangyoon Lee 006; Jaewook Kim; Suhwan Kim 001; Joo-Hyung Chae (IEEE J. Solid State Circuits, 2021)

Design and Comparative Study of Voltage Regulation-Based 2-Tap Flexible Feed-Forward Equalizer for Voltage-Mode Transmitters. - Joo-Hyung Chae; Yong-Un Jeong; Byung-Du Choi (IEEE Access, 2022)

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. - Jihyo Kang; Jaehyeok Yang; Kyunghoon Kim; Joo-Hyung Chae; Gang-Sik Lee; Sang-Yeon Byeon; Boram Kim; Dong-Hyun Kim; Youngtaek Kim; Yeongmuk Cho; Junghwan Ji; Sera Jeong; et al. (IEEE J. Solid State Circuits, 2022)

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. - Yong-Un Jeong; Sungphil Choi; Joo-Hyung Chae; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching. - Sangyoon Lee 006; Yong-Un Jeong; Jaekwang Yun; Joo-Hyung Chae; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Module Implementation and Simulation of Timing Constraint Check Function of I2C Protocol Using Verilog. - Jun-Cheol Lee; Tae-Oh Kim; Joo-Hyung Chae (ICEIC, 2023)

A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line. - Jaewook Kim; Jaekwang Yun; Joo-Hyung Chae; Suhwan Kim 001 (IEEE Access, 2023)

Design of Clocked Comparator Preventing Bit Errors to Improve Reliability of Low-Speed DRAM Measurement. - Joo-Hyung Chae (IEEE Trans. Instrum. Meas., 2023)

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces. - Yong-Un Jeong; Joo-Hyung Chae; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2023)

Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. - Yong-Un Jeong; Sungphil Choi; Suhwan Kim 001; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 1-Kb 6T 1C XNOR-DRAM Compute-In-Memory Macro With Signed Bit Adder Block for CNN Operations. - Ho-Sung Lee; Joo-Hyung Chae (ICEIC, 2024)

A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes. - Hyeonjun Cheon; Ho-Sung Lee; Jiwon Lee; Ik-Hyeon Jeon; Joo-Hyung Chae (ISOCC, 2024)

Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed. - Jiwon Lee; Hyeonjun Cheon; Ho-Sung Lee; Ik-Hyeon Jeon; Joo-Hyung Chae (ISOCC, 2024)

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency. - Chanheum Han; Ki-Soo Lee; Joo-Hyung Chae (ISSCC, 2024)

Debugging Circuit for Detecting Timing Errors in Serializer for High-Speed Wireline Interfaces. - Jongchan Lee; Joo-Hyung Chae (IEEE Access, 2024)

Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces. - Yong-Un Jeong; Joo-Hyung Chae (IEEE Trans. Instrum. Meas., 2024)

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces. - Jaekwang Yun; Sangyoon Lee 006; Jaewook Kim; Joo-Hyung Chae; Suhwan Kim 001; Yong-Un Jeong (IEEE J. Solid State Circuits, 2024)

A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces. - Yong-Un Jeong; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.9-V 15.6-Gb/s Single Ended NRZ Receiver with 1-Tap DFE for Low-Power Memory Interfaces. - Jongmin Lee; Ki-Soo Lee; Joo-Hyung Chae (ICEIC, 2025)

A 1.05-V/0.5-V 15.6-Gb/s NRZ Transmitter Achieving 0.76-pJ/bit Energy Efficiency for Low-Power Memory Interfaces. - Ju-Hyeong Yun; Yong-Gyu Yu; Jongchan Lee; Joo-Hyung Chae (ICEIC, 2025)

SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver. - Chae-Hyeon Lim; Ju-Hyeong Yun; Yong-Gyu Yu; Joo-Hyung Chae (SMACD, 2025)

SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4. - Yong-Gyu Yu; Ju-Hyeong Yun; Chae-Hyeon Lim; Joo-Hyung Chae (SMACD, 2025)

URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros. - Ho-Sung Lee; Ik-Hyeon Jeon; Jiwon Lee; Hyeonjun Cheon; Joo-Hyung Chae (IEEE Access, 2025)

25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies. - Chanheum Han; Ki-Soo Lee; Joo-Hyung Chae (IEEE J. Solid State Circuits, 2025)

A VM-Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces. - Chanheum Han; Ki-Soo Lee; Jun-Cheol Lee; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing. - Ik-Hyeon Jeon; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)