A quantization noise cancelling fractional-N type ΔΣ frequency synthesizer using SAR-based DAC gain calibration. - Seungjin Kim; In-Young Lee; Joo-Myoung Kim; Sang-Gug Lee 001 (CICC, 2012)

A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology. - Joo-Myoung Kim; Seungjin Kim; In-Young Lee; Seok-Kyun Han; Sang-Gug Lee 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS. - Joo-Myoung Kim; Jae-Seung Lee; Sun-a Kim; Taeik Kim; Hojin Park; Sang-Gug Lee 001 (CICC, 2015)

13.1 A 227pJ/b -83dBm 2.4GHz multi-channel OOK receiver adopting receiver-based FLL. - Jae-Seung Lee; Joo-Myoung Kim; Jaesup Lee; Seok-Kyun Han; Sang-Gug Lee 001 (ISSCC, 2015)

0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing. - Sun-a Kim; Kyoung-Yong Choi; Dae-Woong Park; Joo-Myoung Kim; Seok-Kyun Han; Sang-Gug Lee 001 (A-SSCC, 2017)

A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration. - Jaehong Jung; Seunghyun Oh; Joo-Myoung Kim; Gihyeok Ha; Jinhyeon Lee; Seungjin Kim; Euiyoung Park; Jaehoon Lee 005; Yelim Yoon; Seungyong Bae; Wonkang Kim; Yong Lim; et al. (ISSCC, 2022)

A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS. - Kyungmin Lee; Jaehong Jung; Gyusik Kim; Joomyoung Kim; Seungjin Kim; Seunghyun Oh; Sung Min Park 001; Jongwoo Lee (A-SSCC, 2023)

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)

A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS. - Jaehong Jung; Seunghyun Oh; Joomyoung Kim; Jinhyeon Lee; Wonkang Kim; Euiyoung Park; Seungyong Bae; Seungjin Kim; Jaehoon Lee 005; Yelim Youn; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)