A Multi-Nodes Human Body Communication Sensor Network Control Processor. - Sungdae Choi; Seong-Jun Song; Kyomin Sohn; Hyejung Kim; Joo-Young Kim 001; Namjun Cho; Jeong-Ho Woo; Jerald Yoo; Hoi-Jun Yoo (CICC, 2006)

A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS. - Joo-Young Kim 001; Kangmin Lee; Hoi-Jun Yoo (ISCAS, 2006)

An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control. - Sungdae Choi; Kyomin Sohn; Hyejung Kim; Joo-Young Kim 001; Seong-Jun Song; Namjun Cho; Jerald Yoo; Hoi-Jun Yoo (SoC, 2006)

A Low-power Star-topology Body Area Network Controller for Periodic Data Monitoring Around and Inside the Human Body. - Sungdae Choi; Seong-Jun Song; Kyomin Sohn; Hyejung Kim; Joo-Young Kim 001; Jerald Yoo; Hoi-Jun Yoo (ISWC, 2006)

An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (CICC, 2007)

Visual image processing RAM for fast 2-D data location search. - Joo-Young Kim 001; Donghyun Kim 014; Seungjin Lee 001; Kwanho Kim; Seonghyun Jeon; Hoi-Jun Yoo (ESSCIRC, 2007)

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (NOCS, 2007)

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (DAC, 2008)

A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip. - Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Minsu Kim 004; Hoi-Jun Yoo (ESSCIRC, 2008)

A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects. - Joonsung Bae; Joo-Young Kim 001; Hoi-Jun Yoo (ISCAS, 2008)

A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine. - Kwanho Kim; Seungjin Lee 001; Joo-Young Kim 001; Minsu Kim 004; Donghyun Kim 014; Jeong-Ho Woo; Hoi-Jun Yoo (ISSCC, 2008)

A 54GOPS 51.8mW analog-digital mixed mode Neural Perception Engine for fast object detection. - Minsu Kim 004; Joo-Young Kim 001; Seungjin Lee 001; Jinwook Oh; Hoi-Jun Yoo (CICC, 2009)

A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor. - Joo-Young Kim 001; Kwanho Kim; Seungjin Lee 001; Minsu Kim 004; Jinwook Oh; Hoi-Jun Yoo (ESSCIRC, 2009)

A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management. - Joo-Young Kim 001; Seungjin Lee 001; Jinwook Oh; Minsu Kim 004; Hoi-Jun Yoo (ISLPED, 2009)

A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine. - Joo-Young Kim 001; Minsu Kim 004; Seungjin Lee 001; Jinwook Oh; Kwanho Kim; Sejong Oh; Jeong-Ho Woo; Donghyun Kim 014; Hoi-Jun Yoo (ISSCC, 2009)

Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Hoi-Jun Yoo (IET Comput. Digit. Tech., 2009)

A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine. - Kwanho Kim; Seungjin Lee 001; Joo-Young Kim 001; Minsu Kim 004; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2009)

Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining. - Joo-Young Kim 001; Minsu Kim 004; Seungjin Lee 001; Jinwook Oh; Sejong Oh; Hoi-Jun Yoo (IEEE Micro, 2009)

A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition. - Kwanho Kim; Seungjin Lee 001; Joo-Young Kim 001; Minsu Kim 004; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. Video Technol., 2009)

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC. - Donghyun Kim 014; Kwanho Kim; Joo-Young Kim 001; Seungjin Lee 001; Se-Joong Lee; Hoi-Jun Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Intelligent NoC with neuro-fuzzy bandwidth regulation for a 51 IP object recognition processor. - Seungjin Lee 001; Jinwook Oh; Minsu Kim 004; Junyoung Park 002; Joonsoo Kwon; Joo-Young Kim 001; Hoi-Jun Yoo (CICC, 2010)

A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine. - Joo-Young Kim 001; Minsu Kim 004; Seungjin Lee 001; Jinwook Oh; Kwanho Kim; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2010)

A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition. - Joo-Young Kim 001; Junyoung Park 002; Seungjin Lee 001; Minsu Kim 004; Jinwook Oh; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2010)

Familiarity based unified visual attention model for fast and robust object recognition. - Seungjin Lee 001; Kwanho Kim; Joo-Young Kim 001; Minsu Kim 004; Hoi-Jun Yoo (Pattern Recognit., 2010)

An attention controlled multi-core architecture for energy efficient object recognition. - Joo-Young Kim 001; Sejong Oh; Seungjin Lee 001; Minsu Kim 004; Jinwook Oh; Hoi-Jun Yoo (Signal Process. Image Commun., 2010)

Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor. - Joo-Young Kim 001; Donghyun Kim 014; Seungjin Lee 001; Kwanho Kim; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. Video Technol., 2010)

24-GOPS 4.5-mm2 Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC. - Seungjin Lee 001; Minsu Kim 004; Kwanho Kim; Joo-Young Kim 001; Hoi-Jun Yoo (IEEE Trans. Neural Networks, 2011)

A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource management. - Jinwook Oh; Gyeonghoon Kim; Junyoung Park 002; Injoon Hong; Seungjin Lee 001; Joo-Young Kim 001; Hoi-Jun Yoo (COOL Chips, 2012)

A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine. - Junyoung Park 002; Joonsoo Kwon; Jinwook Oh; Seungjin Lee 001; Joo-Young Kim 001; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2012)

Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems. - Jinwook Oh; Gyeonghoon Kim; Injoon Hong; Junyoung Park 002; Seungjin Lee 001; Joo-Young Kim 001; Jeong-Ho Woo; Hoi-Jun Yoo (IEEE Micro, 2012)

A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams. - Jinwook Oh; Gyeonghoon Kim; Junyoung Park 002; Injoon Hong; Seungjin Lee 001; Joo-Young Kim 001; Jeong-Ho Woo; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2013)

Energy efficient canonical huffman encoding. - Janarbek Matai; Joo-Young Kim 001; Ryan Kastner (ASAP, 2014)

A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer. - Joo-Young Kim 001; Scott Hauck; Doug Burger (FCCM, 2014)

A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs. - Jeremy Fowers; Joo-Young Kim 001; Doug Burger; Scott Hauck (FCCM, 2015)

Toward accelerating deep learning at scale using specialized hardware in the datacenter. - Kalin Ovtcharov; Olatunji Ruwase; Joo-Young Kim 001; Jeremy Fowers; Karin Strauss; Eric S. Chung (Hot Chips Symposium, 2015)

A cloud-scale acceleration architecture. - Adrian M. Caulfield; Eric S. Chung; Andrew Putnam; Hari Angepat; Jeremy Fowers; Michael Haselman; Stephen Heil; Matt Humphrey; Puneet Kaur; Joo-Young Kim 001; Daniel Lo; Todd Massengill; et al. (MICRO, 2016)

A reconfigurable fabric for accelerating large-scale datacenter services. - Andrew Putnam; Adrian M. Caulfield; Eric S. Chung; Derek Chiou; Kypros Constantinides; John Demme; Hadi Esmaeilzadeh; Jeremy Fowers; Gopi Prashanth Gopal; Jan Gray; Michael Haselman; Scott Hauck; et al. (Commun. ACM, 2016)

Configurable Clouds. - Adrian M. Caulfield; Eric S. Chung; Andrew Putnam; Hari Angepat; Daniel Firestone; Jeremy Fowers; Michael Haselman; Stephen Heil; Matt Humphrey; Puneet Kaur; Joo-Young Kim 001; Daniel Lo; et al. (IEEE Micro, 2017)

Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision. - Ji-Hoon Kim 004; Juhyoung Lee; Jinsu Lee; Hoi-Jun Yoo; Joo-Young Kim 001 (VLSI Circuits, 2020)

FIXAR: A Fixed-Point Deep Reinforcement Learning Platform with Quantization-Aware Training and Adaptive Parallelism. - Je Yang; Seongmin Hong; Joo-Young Kim 001 (DAC, 2021)

Accelerating Large-Scale Nearest Neighbor Search with Computational Storage Device. - Ji-Hoon Kim 004; Yeo-Reum Park; Jaeyoung Do; Soo Young Ji; Joo-Young Kim 001 (FCCM, 2021)

Chapter Five - FPGA based neural network accelerators. - Joo-Young Kim 001 (Adv. Comput., 2021)

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. - Ji-Hoon Kim 004; Juhyoung Lee; Jinsu Lee; Jaehoon Heo; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2021)

T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training. - Jaehoon Heo; Junsoo Kim 002; Wontak Han; Sukbin Lim; Joo-Young Kim 001 (CICC, 2022)

A Dual-Mode Similarity Search Accelerator based on Embedding Compression for Online Cross-Modal Image-Text Retrieval. - Yeo-Reum Park; Ji-Hoon Kim 004; Jaeyoung Do; Joo-Young Kim 001 (FCCM, 2022)

OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Multi-Die FPGAs. - Gyeongcheol Shin; Junsoo Kim 002; Joo-Young Kim 001 (FCCM, 2022)

FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure. - Yashael Faith Arthanto; David Ojika; Joo-Young Kim 001 (FPL, 2022)

LearningGroup: A Real-Time Sparse Training on FPGA via Learnable Weight Grouping for Multi-Agent Reinforcement Learning. - Je Yang; Jaeuk Kim; Joo-Young Kim 001 (FPT, 2022)

DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation. - Seongmin Hong; Seungjae Moon; Junsoo Kim 002; Sungjae Lee 002; Minsub Kim; Dongsoo Lee; Joo-Young Kim 001 (HCS, 2022)

Trinity: End-to-End In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data Analytics. - Ji-Hoon Kim 004; Seunghee Han; Kwanghyun Park 001; Soo-Young Ji; Joo-Young Kim 001 (HCS, 2022)

LightTrader : World's first AI-enabled High-Frequency Trading Solution with 16 TFLOPS / 64 TOPS Deep Learning Inference Accelerators. - Hyunsung Kim 003; Sungyeob Yoo; Jaewan Bae; Kyeongryeol Bong; Yoonho Boo; Karim Charfi; Hyo-Eun Kim; Hyun Suk Kim; Jinseok Kim 006; Byungjae Lee; Jaehwan Lee; Myeongbo Shim; et al. (HCS, 2022)

Federated Onboard-Ground Station Computing With Weakly Supervised Cascading Pyramid Attention Network for Satellite Image Analysis. - Taewoo Kim 003; Minsu Jeon; Changha Lee; Junsoo Kim 002; Geonwoo Ko; Joo-Young Kim 001; Chan-Hyun Youn (IEEE Access, 2022)

OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs. - Gyeongcheol Shin; Junsoo Kim 002; Joo-Young Kim 001 (IEEE Comput. Archit. Lett., 2022)

Exploration of Systolic-Vector Architecture with Resource Scheduling for Dynamic ML Workloads. - Jung-Hoon Kim; Sungyeob Yoo; Seungjae Moon; Joo-Young Kim 001 (CoRR, 2022)

Accelerating Large-Scale Graph-based Nearest Neighbor Search on a Computational Storage Platform. - Ji-Hoon Kim 004; Yeo-Reum Park; Jaeyoung Do; Soo Young Ji; Joo-Young Kim 001 (CoRR, 2022)

Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training. - Wontak Han; Jaehoon Heo; Junsoo Kim 002; Sukbin Lim; Joo-Young Kim 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Guest Editorial Revolution of AI and Machine Learning With Processing-in-Memory (PIM): From Systems, Architectures, to Circuits. - Tony Tae-Hyoung Kim; Bongjin Kim; Joo-Young Kim 001; Jaydeep P. Kulkarni (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning. - Donghyuk Kim; Chengshuo Yu; Shanshan Xie; Yuzong Chen 001; Joo-Young Kim 001; Bongjin Kim; Jaydeep P. Kulkarni; Tony Tae-Hyoung Kim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 26.55TOPS/W Explainable AI Processor with Dynamic Workload Allocation and Heat Map Compression/Pruning. - Junsoo Kim 002; Geonwoo Ko; Ji-Hoon Kim 004; Changha Lee; Taewoo Kim 003; Chan-Hyun Youn; Joo-Young Kim 001 (CICC, 2023)

JNPU: A 1.04TFLOPS Joint-DNN Training Processor with Speculative Cyclic Quantization and Triple Heterogeneity on Microarchitecture / Precision / Dataflow. - Je Yang; Sukbin Lim; Sukjin Lee; Jae-Young Kim; Joo-Young Kim 001 (ESSCIRC, 2023)

LightTrader: A Standalone High-Frequency Trading System with Deep Learning Inference Accelerators and Proactive Scheduler. - Sungyeob Yoo; Hyunsung Kim 003; Jinseok Kim 006; Sunghyun Park; Joo-Young Kim 001; Jinwook Oh (HPCA, 2023)

PRIMO: A Full-Stack Processing-in-DRAM Emulation Framework for Machine Learning Workloads. - Jaehoon Heo; Yongwon Shin; Sangjin Choi; Sungwoong Yune; Jung-Hoon Kim; Hyojin Sung; Youngjin Kwon; Joo-Young Kim 001 (ICCAD, 2023)

Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping. - Adiwena Putra; Prasetiyo; Yi Chen; John Kim 001; Joo-Young Kim 001 (MICRO, 2023)

SP-PIM: A 22.41TFLOPS/W, 8.81Epochs/Sec Super-Pipelined Processing-In-Memory Accelerator with Local Error Prediction for On-Device Learning. - Jung-Hoon Kim; Jaehoon Heo; Wontak Han; Jaeuk Kim; Joo-Young Kim 001 (VLSI Technology and Circuits, 2023)

Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics. - Donghyuk Kim; Jae-Young Kim; Wontak Han; Jongsoon Won; Haerang Choi; Yongkee Kwon; Joo-Young Kim 001 (CoRR, 2023)

Accelerating Large-Scale Graph-Based Nearest Neighbor Search on a Computational Storage Platform. - Ji-Hoon Kim 004; Yeo-Reum Park; Jaeyoung Do; Soo-Young Ji; Joo-Young Kim 001 (IEEE Trans. Computers, 2023)

Agamotto: A Performance Optimization Framework for CNN Accelerator With Row Stationary Dataflow. - Donghyuk Kim; Sanghyun Jeong; Joo-Young Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform. - Prasetiyo; Seongmin Hong; Yashael Faith Arthanto; Joo-Young Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training. - Jaehoon Heo; Junsoo Kim 002; Sukbin Lim; Wontak Han; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2023)

South Korea's Nationwide Effort for AI Semiconductor Industry. - Ji-Hoon Kim 004; Sungyeob Yoo; Joo-Young Kim 001 (Commun. ACM, 2023)

Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC). - SeongHwan Cho; Joo-Young Kim 001; Minoru Fujishima; Jun Zhou 017 (IEEE J. Solid State Circuits, 2023)

ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile Robots. - Jinho Yang; Sungwoong Yune; Sukbin Lim; Donghyuk Kim; Joo-Young Kim 001 (ASPDAC, 2024)

A 38.5TOPS/W Point Cloud Neural Network Processor with Virtual Pillar and Quadtree-based Workload Management for Real-Time Outdoor BEV Detection. - Sukbin Lim; Jaehoon Heo; Jinho Yang; Joo-Young Kim 001 (CICC, 2024)

Picasso: An Area/Energy-Efficient End-to-End Diffusion Accelerator with Hyper-Precision Data Type. - Sungyeob Yoo; Geonwoo Ko; Seri Ham; Seeyeon Kim; Yi Chen; Joo-Young Kim 001 (HCS, 2024)

Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse. - Prasetiyo; Adiwena Putra; Joo-Young Kim 001 (HPCA, 2024)

APINT: A Full-Stack Framework for Acceleration of Privacy-Preserving Inference of Transformers based on Garbled Circuits. - Hyunjun Cho; Jaeho Jeon; Jaehoon Heo; Joo-Young Kim 001 (ICCAD, 2024)

BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing. - Seunghee Han; Seungjae Moon; Teokkyu Suh; Jaehoon Heo; Joo-Young Kim 001 (ISCA, 2024)

AdapTiV: Sign-Similarity Based Image-Adaptive Token Merging for Vision Transformer Acceleration. - Seungjae Yoo; Hangyeol Kim; Joo-Young Kim 001 (MICRO, 2024)

Trinity: In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data Analytics. - Ji-Hoon Kim 004; Seunghee Han; Kwanghyun Park 001; Soo-Young Ji; Joo-Young Kim 001 (IEEE Access, 2024)

HURRY: Highly Utilized, Reconfigurable ReRAM-based In-situ Accelerator with Multifunctionality. - Hery Shin; Jae-Young Kim; Donghyuk Kim; Joo-Young Kim 001 (CoRR, 2024)

A Latency Processing Unit: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference. - Seungjae Moon; Jung-Hoon Kim; Junsoo Kim 002; Seongmin Hong; Junseo Cha; Minsu Kim 004; Sukbin Lim; Gyubin Choi; Dongjin Seo; Jongho Kim; Hunjong Lee; Hyunjun Park; et al. (IEEE Micro, 2024)

EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning. - Junsoo Kim 002; Seunghee Han; Geonwoo Ko; Ji-Hoon Kim 004; Changha Lee; Taewoo Kim 003; Chan-Hyun Youn; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2024)

SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning. - Jaehoon Heo; Jung-Hoon Kim; Wontak Han; Jaeuk Kim; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2024)

A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS. - Yuli Han; Jaemin Kim; Gunmo Koo; Jaejin Kim; Jusung Kim; Joo-Young Kim 001; Kunhee Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

AoP-SAM: Automation of Prompts for Efficient Segmentation. - Yi Chen; Muyoung Son; Chuanbo Hua; Joo-Young Kim 001 (AAAI, 2025)

EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models. - Jaehoon Heo; Adiwena Putra; Jieon Yoon; Sungwoong Yune; Hangyeol Lee; Ji-Hoon Kim 004; Joo-Young Kim 001 (HPCA, 2025)

Oaken: Fast and Efficient LLM Serving with Online-Offline Hybrid KV Cache Quantization. - Minsu Kim 004; Seongmin Hong; Ryeowook Ko; Soongyu Choi; Hunjong Lee; Junsoo Kim 002; Joo-Young Kim 001; Jongse Park (ISCA, 2025)

LightNobel: Improving Sequence Length Limitation in Protein Structure Prediction Model via Adaptive Activation Quantization. - Seunghee Han; Soongyu Choi; Joo-Young Kim 001 (ISCA, 2025)

Hybe: GPU-NPU Hybrid System for Efficient LLM Inference with Million-Token Context Window. - Seungjae Moon; Junseo Cha; Hyunjun Park; Joo-Young Kim 001 (ISCA, 2025)

ADOR: A Design Exploration Framework for LLM Serving with Enhanced Latency and Throughput. - Junsoo Kim 002; Hunjong Lee; Geonwoo Ko; Gyubin Choi; Seri Ham; Seongmin Hong; Joo-Young Kim 001 (ISPASS, 2025)

23.10 HuMoniX: A 57.3fps 12.8TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity. - Jaehoon Heo; Adiwena Putra; Sungwoong Yune; Jieon Yoon; Hangyeol Lee; Jihoon Kim; Joo-Young Kim 001 (ISSCC, 2025)

SuFP: Piecewise Bit Allocation Floating-Point for Robust Neural Network Quantization. - Geonwoo Ko; Sungyeob Yoo; Seri Ham; Seeyeon Kim; Minkyu Kim; Joo-Young Kim 001 (Trans. Mach. Learn. Res., 2025)

Securing DRAM at Scale: ARFM-Driven Row Hammer Defense with Unveiling the Threat of Short tRC Patterns. - Nogeun Joo; Donghyuk Kim; Hyunjun Cho; Junseok Noh; Dongha Jung; Joo-Young Kim 001 (CoRR, 2025)

RED: Energy Optimization Framework for eDRAM-based PIM with Reconfigurable Voltage Swing and Retention-aware Scheduling. - Jae-Young Kim; Donghyuk Kim; Seungjae Yoo; Sungyeob Yoo; Teokkyu Suh; Joo-Young Kim 001 (CoRR, 2025)

Hawkeye: A Point Cloud Neural Network Processor With Virtual Pillar and Quadtree-Based Workload Management for Real-Time Outdoor BEV Detection. - Sukbin Lim; Jaehoon Heo; Jinho Yang; Joo-Young Kim 001 (IEEE J. Solid State Circuits, 2025)

SCRec: A Scalable Computational Storage System with Statistical Sharding and Tensor-train Decomposition for Recommendation Models. - Jinho Yang; Ji-Hoon Kim 004; Joo-Young Kim 001 (CoRR, 2025)

ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption. - Sungwoong Yune; Hyojeong Lee; Adiwena Putra; Hyunjun Cho; Cuong Duong Manh; Jaeho Jeon; Joo-Young Kim 001 (CoRR, 2025)

SAL-PIM: A Subarray-Level Processing-in-Memory Architecture With LUT-Based Linear Interpolation for Transformer-Based Text Generation. - Wontak Han; Hyunjun Cho; Donghyuk Kim; Joo-Young Kim 001 (IEEE Trans. Computers, 2025)