Efficient VLSI implementation of inverse discrete cosine transform [image coding applications]. - Jooheung Lee; Narayanan Vijaykrishnan; Mary Jane Irwin (ICASSP (5), 2004)

An Architecture for Motion Estimation in the Transform Domain. - Jooheung Lee; Narayanan Vijaykrishnan; Mary Jane Irwin; Wayne H. Wolf (VLSI Design, 2004)

High Performance Array Processor for Video Decoding. - Jooheung Lee; Narayanan Vijaykrishnan; Mary Jane Irwin (ISVLSI, 2005)

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. - Jooheung Lee; Narayanan Vijaykrishnan; Mary Jane Irwin (IEEE Trans. Circuits Syst. Video Technol., 2006)

An efficient architecture for motion estimation and compensation in the transform domain. - Jooheung Lee; Narayanan Vijaykrishnan; Mary Jane Irwin; Wayne H. Wolf (IEEE Trans. Circuits Syst. Video Technol., 2006)

Block-based frequency scalable technique for efficient hierarchical coding. - Jooheung Lee; Narayanan Vijaykrishnan; Mary Jane Irwin; Rajarathnam Chandramouli (IEEE Trans. Signal Process., 2006)

A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field. - Jian Huang; Jooheung Lee; Hao Li (Security and Management, 2008)

Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration. - Jian Huang; Matthew Parris; Jooheung Lee; Ronald F. DeMara (ERSA, 2008)

Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study. - Yidong Liu; Srinivasan Santhanam; Jooheung Lee (ERSA, 2008)

A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration. - Sumedha Gupta Kodipyaka; Jooheung Lee (ERSA, 2009)

Efficient VLSI architecture for video transcoding. - Jian Huang; Jooheung Lee (IEEE Trans. Consumer Electron., 2009)

A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching. - Jian Huang; Jooheung Lee (IEEE Trans. Circuits Syst. Video Technol., 2009)

Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. - Jian Huang; Matthew Parris; Jooheung Lee; Ronald F. DeMara (ACM Trans. Embed. Comput. Syst., 2009)

Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors. - Ronald F. DeMara; Jooheung Lee; Rawad N. Al-Haddad; Rashad S. Oreifej; Rizwan A. Ashraf; Brian Stensrud; Michael Quist (ERSA, 2010)

A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration. - Rakan Khraisha; Jooheung Lee (ICASSP, 2010)

Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation. - Jian Huang; Jooheung Lee (IEEE Embed. Syst. Lett., 2011)

Error surface-aware modeling algorithm for quarter-pixel motion estimation. - Junsang Cho; Jungwook Suh; Gwanggil Jeon; Jooheung Lee; Jechang Jeong (IEEE Trans. Consumer Electron., 2012)

A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration. - Rakan Khraisha; Jooheung Lee (J. Signal Process. Syst., 2012)

Fault Demotion Using Reconfigurable Slack (FaDReS). - Naveed Imran; Jooheung Lee; Ronald F. DeMara (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Self-Adapting Resource Escalation for Resilient Signal Processing Architectures. - Naveed Imran; Ronald F. DeMara; Jooheung Lee; Jian Huang (J. Signal Process. Syst., 2014)

Activity-Based Resource Allocation for Motion Estimation Engines. - Naveed Imran; Rizwan A. Ashraf; Jooheung Lee; Ronald F. DeMara (J. Circuits Syst. Comput., 2015)

Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences. - Iljung Yoon; Heewon Joung; Jooheung Lee (J. Sensors, 2016)

Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC. - Iljung Yoon; Anand Paul 001; Jooheung Lee (Intell. Autom. Soft Comput., 2017)

Energy efficient processing of motion estimation for embedded multimedia systems. - Jooheung Lee (Multim. Tools Appl., 2017)

Write-Amount-Aware Management Policies for STT-RAM Caches. - Hyeonggyu Kim; Soontae Kim; Jooheung Lee (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hardware Multi-Threaded System for High-Performance JPEG Decoding. - Hyeonjun Shin; Jooheung Lee (J. Signal Process. Syst., 2024)