Single cycle access cache for the misaligned data and instruction prefetch. - Joon-Seo Yim; Hee-Choul Lee; Tae-Hoon Kim; Bong-Il Park; Chang-Jae Park; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1997)

Verification methodology of compatible microprocessors. - Joon-Seo Yim; Chang-Jae Park; Woo-Seung Yang; Hun-Seung Oh; Hee-Choul Lee; Hoon Choi; Tae-Hoon Kim; Seungjong Lee; Nara Won; Yung-Hei Lee; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1997)

A C-Based RTL Design Verification Methodology for Complex Microprocessor. - Joon-Seo Yim; Yoon-Ho Hwang; Chang-Jae Park; Hoon Choi; Woo-Seung Yang; Hun-Seung Oh; In-Cheol Park; Chong-Min Kyung (DAC, 1997)

Design Verification of Complex Microprocessors. - Joon-Seo Yim; Chang-Jae Park; In-Cheol Park; Chong-Min Kyung (J. Circuits Syst. Comput., 1997)

A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs. - Joon-Seo Yim; Seong-Ok Bae; Chong-Min Kyung (DAC, 1999)

Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design. - Joon-Seo Yim; Chong-Min Kyung (DAC, 1999)