Power optimizations for transport triggered SIMD processors. - Joonas Multanen; Timo Viitanen; Henry Linjamaki; Heikki Kultala; Pekka Jääskeläinen; Jarmo Takala; Lauri Koskinen; Jesse Simonsson; Heikki Berg; Kalle Raiskila; Tommi Zetterman (SAMOS, 2015)

Customized high performance low power processor for binaural speaker localization. - Nicolai Behmann; Christopher Seifert; Guillermo Payá-Vayá; Holger Blume; Pekka Jääskeläinen; Joonas Multanen; Heikki Kultala; Jarmo Takala; Joachim Thiemann; Steven van de Par (ICECS, 2016)

OpenCL programmable exposed datapath high performance low-power image signal processor. - Joonas Multanen; Heikki Kultala; Matias Koskela; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala; Aram Danielyan; Cristóvão Cruz (NORCAS, 2016)

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies. - Joonas Multanen; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (SiPS, 2016)

Foveated instant preview for progressive rendering. - Matias Koskela; Kalle Immonen; Timo Viitanen; Pekka Jääskeläinen; Joonas Multanen; Jarmo Takala (SIGGRAPH Asia Technical Briefs, 2017)

Energy-Delay Trade-Offs in Instruction Register File Design. - Joonas Multanen; Heikki Kultala; Pekka Jääskeläinen (NORCAS, 2018)

LoTTA: Energy-Efficient Processor for Always-On Applications. - Joonas Multanen; Heikki Kultala; Pekka Jääskeläinen; Timo Viitanen; Aleksi Tervo; Jarmo Takala (SiPS, 2018)

Instantaneous foveated preview for progressive Monte Carlo rendering. - Matias Koskela; Kalle Immonen; Timo Viitanen; Pekka Jääskeläinen; Joonas Multanen; Jarmo H. Takala (Comput. Vis. Media, 2018)

Instruction Fetch Energy Reduction with Biased SRAMs. - Joonas Multanen; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (J. Signal Process. Syst., 2018)

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. - Joonas Multanen; Pekka Jääskeläinen; Asif Ali Khan; Fazal Hameed; Jerónimo Castrillón (ISLPED, 2019)

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor. - Heikki Kultala; Timo Viitanen; Heikki Berg; Pekka Jääskeläinen; Joonas Multanen; Mikko Kokkonen; Kalle Raiskila; Tommi Zetterman; Jarmo Takala (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency. - Joonas Multanen; Kari Hepola; Pekka Jääskeläinen (ICCD, 2020)

System Simulation of Memristor Based Computation in Memory Platforms. - Ali BanaGozar; Kanishkan Vadivel; Joonas Multanen; Pekka Jääskeläinen; Sander Stuijk; Henk Corporaal (SAMOS, 2020)

Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications. - Joonas Multanen; Heikki Kultala; Kati Tervo; Pekka Jääskeläinen (J. Signal Process. Syst., 2020)

Unified OpenCL Integration Methodology for FPGA Designs. - Topi Leppänen; Panagiotis Mousouliotis; Georgios Keramidas; Joonas Multanen; Pekka Jääskeläinen (NorCAS, 2021)

Energy-Efficient Instruction Streams for Embedded Processors. - Joonas Multanen (2021)

Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (ARCS, 2022)

OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (ASAP, 2022)

Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory. - Joonas Multanen; Kari Hepola; Asif Ali Khan; Jerónimo Castrillón; Pekka Jääskeläinen (IEEE Trans. Computers, 2022)

AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management. - Topi Leppänen; Joonas Multanen; Leevi Leppänen; Pekka Jääskeläinen (NorCAS, 2023)

Efficient OpenCL system integration of non-blocking FPGA accelerators. - Topi Leppänen; Atro Lotvonen; Panagiotis Mousouliotis; Joonas Multanen; Georgios Keramidas; Pekka Jääskeläinen (Microprocess. Microsystems, 2023)

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors. - Alex Hirvonen; Topi Leppänen; Kari Hepola; Joonas Multanen; Joost Hoozemans; Pekka Jääskeläinen (J. Signal Process. Syst., 2023)

Towards Efficient OpenCL Pipe Specification for Hardware Accelerators. - Topi Leppänen; Joonas Multanen; Leevi Leppänen; Pekka Jääskeläinen (IWOCL, 2024)

Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions. - Kari Hepola; Tharaka Ranasinghe Arachchige; Joonas Multanen; Pekka Jääskeläinen (NorCAS, 2024)

Cycle Count Estimation of VLIW Processors Using Machine Learning. - Kari Hepola; Jatan Shrestha; Joonas Multanen; Vivienne Wang; Joni Pajarinen; Pekka Jääskeläinen (NorCAS, 2024)

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (IEEE Trans. Computers, 2024)

Energy-efficient instruction compression with programmable dictionaries. - Joonas Multanen; Barry de Bruin; Henk Corporaal; Pekka Jääskeläinen (Des. Autom. Embed. Syst., 2024)

Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL. - Topi Leppänen; Leevi Leppänen; Joonas Multanen; Pekka Jääskeläinen (IEEE Trans. Very Large Scale Integr. Syst., 2024)