A fault model for function and delay testing. - Joonhwan Yi; John P. Hayes (ETW, 2001)

High -level function and delay testing for digital circuits. - Joonhwan Yi (2002)

The Coupling Model for Function and Delay Faults. - Joonhwan Yi; John P. Hayes (J. Electron. Test., 2005)

Cycle error correction in asynchronous clock modeling for cycle-based simulation. - Junghee Lee; Joonhwan Yi (ASP-DAC, 2006)

High-level delay test generation for modular circuits. - Joonhwan Yi; John P. Hayes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Industrial experience with cycle error computation of cycle-accurate transaction level models. - Junghee Lee; Joonhwan Yi (SoCC, 2007)

A data flow optimization method for high speed MAC processing in an IEEE 802.16m modem. - Kyung Won Kim; Joonhwan Yi; Seong-Jun Oh (IEICE Electron. Express, 2011)

Robust Coupling Delay Test Sets. - Joonhwan Yi; John P. Hayes (J. Electron. Test., 2012)

Power modeling for digital circuits with clock gating. - Joonhwan Yi; Jong-Gyu Kim (IEICE Electron. Express, 2015)

A Receiver-Initiated MAC Protocol for Wireless Sensor Networks Based on Tree Topology. - Inhye Park; Joonhwan Yi; Hyungkeun Lee (Int. J. Distributed Sens. Networks, 2015)

Register grouping for synthesis of clock gating logic. - Inhak Han; Jonggyu Kim; Joonhwan Yi; Youngsoo Shin (ICICDT, 2016)

Modeling and performance analysis for a receiver-initiated MAC protocol in wireless sensor networks. - Joonhwan Yi; Hyungkeun Lee (Int. J. Distributed Sens. Networks, 2016)

An interpolation method for strong barrel lens distortion. - Changwon Choi; Hyungkeun Lee; Joonhwan Yi (Vis. Comput., 2018)